Marko Adžić wrote:
> "Signal wtp cannot be synthesized, bad synchronous description."
And thats only the tip of an iceberg...
First lets get clear what components you have inside a FPGA for your own
Hardware. Its fairly simple, there are only two of them:
1. Logic Cells (LUTs)
2. D-Flipflops
With those two components the synthesizer must try to implement your
hardware description.
And now lets have a look at your code:
1 | elsif(o1'event and o1='1' and e=1)then
|
2 | wtp:='1';
|
3 | e:=0;
|
4 | end if;
|
5 |
|
6 | if(o2'event and o2='1' and q=1)then
|
7 | brnew:=1;
|
8 | wtp:='0';
|
9 | q:=0;
|
10 | :
|
In VHDL a 'event means: implement a D flipflop on the following signals.
So wtp will be implemented as a D flipflop. And what does a D flipflop
look like? How many clock inputs does it have? Whey does the synthesizer
fail trying to implement wtp as a D flipflop?
Going one step back I can say: your description is obviuosly from a
software programmer first time trying to do VHDL. Where did you find
that extensive use of variables? Who told you to use 5 different clocks
in 1 process? Where did you find this curious way to describe clock
enables?