Signal cannot be synthesized

Marko A. OP #3506617
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Hi guys,
I have to write a program in VHDL language in the Xilinx development 
environment, which later need to load the FPGA. Checking syntax (Check 
Syntax) throw a couple of errors. I solve them. Starting procedure 
Configure Device (iMPACT). And then I get the message:
   "Signal wtp cannot be synthesized, bad synchronous description."
Please someone help me. Sorry for bad English. This is my code:

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

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---- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity main is

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    Port ( cp, o1, o2, rst : in  STD_LOGIC;

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           piz, wt : out  STD_LOGIC;

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        seg : out std_logic_vector (6 downto 0);

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        cet : out std_logic_vector (3 downto 0)

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        );

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end main;

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architecture behavioral of main is

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signal broj : integer range 0 to 30;

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signal seg1, seg2 : std_logic_vector (6 downto 0);

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signal cpd : std_logic;

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begin

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s1 : entity work.djelitelj port map(cp, cpd);

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s2 : entity work.buzzer port map(cp, broj, piz);

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s3 : entity work.numbers port map(cp, broj, seg1, seg2);

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s4 : entity work.display port map(cp, seg1, seg2, seg, cet);

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process(cp, o1, o2, rst)

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variable e, q : integer range 0 to 2;

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variable wtp : std_logic;

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variable brnew : integer range -30 to 30;

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begin

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if(rst'event and rst='1')then 

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   brnew:=-broj;

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end if;

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if(o1'event and o1='1' and e=0)then

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   q:=1;

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elsif(o1'event and o1='1' and e=1)then

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   wtp:='1';  

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  e:=0;

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end if;  

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if(o2'event and o2='1' and q=1)then

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   brnew:=1;

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  wtp:='0';

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  q:=0;

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elsif(o2'event and o2='1' and q=0)then

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   e:=1;

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end if;  

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wt<=wtp;

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broj<=broj+brnew;

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brnew:=0;

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end process;

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end behavioral;
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Lothar M. Moderator (Company: Titel) #3506688
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Marko Adžić wrote:
> "Signal wtp cannot be synthesized, bad synchronous description."
And thats only the tip of an iceberg...

First lets get clear what components you have inside a FPGA for your own 
Hardware. Its fairly simple, there are only two of them:
1. Logic Cells (LUTs)
2. D-Flipflops
With those two components the synthesizer must try to implement your 
hardware description.

And now lets have a look at your code:
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elsif(o1'event and o1='1' and e=1)then

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   wtp:='1';  

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   e:=0;

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end if;  

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if(o2'event and o2='1' and q=1)then

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   brnew:=1;

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   wtp:='0';

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   q:=0;

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:

In VHDL a 'event means: implement a D flipflop on the following signals. 
So wtp will be implemented as a D flipflop. And what does a D flipflop 
look like? How many clock inputs does it have? Whey does the synthesizer 
fail trying to implement wtp as a D flipflop?

Going one step back I can say: your description is obviuosly from a 
software programmer first time trying to do VHDL. Where did you find 
that extensive use of variables? Who told you to use 5 different clocks 
in 1 process? Where did you find this curious way to describe clock 
enables?
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