EmbDev.net

Forum: FPGA, VHDL & Verilog Signal cannot be synthesized


von Marko A. (markanjski)


Rate this post
0 useful
not useful
Hi guys,
I have to write a program in VHDL language in the Xilinx development 
environment, which later need to load the FPGA. Checking syntax (Check 
Syntax) throw a couple of errors. I solve them. Starting procedure 
Configure Device (iMPACT). And then I get the message:
   "Signal wtp cannot be synthesized, bad synchronous description."
Please someone help me. Sorry for bad English. This is my code:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
use IEEE.STD_LOGIC_ARITH.ALL;
4
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5
6
---- Uncomment the following library declaration if instantiating
7
---- any Xilinx primitives in this code.
8
--library UNISIM;
9
--use UNISIM.VComponents.all;
10
11
entity main is
12
    Port ( cp, o1, o2, rst : in  STD_LOGIC;
13
           piz, wt : out  STD_LOGIC;
14
        seg : out std_logic_vector (6 downto 0);
15
        cet : out std_logic_vector (3 downto 0)
16
        );
17
end main;
18
19
architecture behavioral of main is
20
signal broj : integer range 0 to 30;
21
signal seg1, seg2 : std_logic_vector (6 downto 0);
22
signal cpd : std_logic;
23
24
25
begin
26
s1 : entity work.djelitelj port map(cp, cpd);
27
s2 : entity work.buzzer port map(cp, broj, piz);
28
s3 : entity work.numbers port map(cp, broj, seg1, seg2);
29
s4 : entity work.display port map(cp, seg1, seg2, seg, cet);
30
31
process(cp, o1, o2, rst)
32
variable e, q : integer range 0 to 2;
33
variable wtp : std_logic;
34
variable brnew : integer range -30 to 30;
35
begin
36
37
if(rst'event and rst='1')then 
38
   brnew:=-broj;
39
end if;
40
41
if(o1'event and o1='1' and e=0)then
42
   q:=1;
43
elsif(o1'event and o1='1' and e=1)then
44
   wtp:='1';  
45
  e:=0;
46
end if;  
47
48
if(o2'event and o2='1' and q=1)then
49
   brnew:=1;
50
  wtp:='0';
51
  q:=0;
52
elsif(o2'event and o2='1' and q=0)then
53
   e:=1;
54
end if;  
55
56
57
58
wt<=wtp;
59
broj<=broj+brnew;
60
brnew:=0;
61
end process;
62
end behavioral;

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
Marko Adžić wrote:
> "Signal wtp cannot be synthesized, bad synchronous description."
And thats only the tip of an iceberg...

First lets get clear what components you have inside a FPGA for your own 
Hardware. Its fairly simple, there are only two of them:
1. Logic Cells (LUTs)
2. D-Flipflops
With those two components the synthesizer must try to implement your 
hardware description.

And now lets have a look at your code:
1
elsif(o1'event and o1='1' and e=1)then
2
   wtp:='1';  
3
   e:=0;
4
end if;  
5
6
if(o2'event and o2='1' and q=1)then
7
   brnew:=1;
8
   wtp:='0';
9
   q:=0;
10
:
In VHDL a 'event means: implement a D flipflop on the following signals. 
So wtp will be implemented as a D flipflop. And what does a D flipflop 
look like? How many clock inputs does it have? Whey does the synthesizer 
fail trying to implement wtp as a D flipflop?

Going one step back I can say: your description is obviuosly from a 
software programmer first time trying to do VHDL. Where did you find 
that extensive use of variables? Who told you to use 5 different clocks 
in 1 process? Where did you find this curious way to describe clock 
enables?

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.