This is code for finding CRC for all combination of inputs. I cheked
this before synthesis which is working fine but after synthesis giving
error as bellow.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity crc1 is
port( clk : in std_logic;
reset: in std_logic;
input1: in std_logic;
output1: out std_logic);
end crc1;
architecture arch of crc1 is
signal count2:integer;
signal b:std_logic_vector(7 downto 0);
begin
process(clk,reset)
begin
if reset = '1' then
count2 <= 0 ;
elsif rising_edge(clk) then
if count2 = 1504 then
count2 <= 1 ;
else
count2 <= count2 + 1 ;
end if;
end if ;
end process ;
process(count2 , reset , b, input1)
variable i: integer range 0 to 8;
begin
if reset ='1' then
b <= "00000000" ;
i := 0;
else
if (count2 > 8 and count2 <= 1504) then
if (b(7)='0') then
b <= b(6 downto 0) & input1;
else
b <= ((b(6 downto 0) & input1) xor "11010101" );
end if;
end if;
end if;
if (count2 >= 1 and count2 <= 8) then
output1 <= b(i);
b(i) <= '0' ;
i:= i + 1;
else
i:= 0;
output1<= input1;
end if;
end process;
end arch;
# ** Error: (vsim-3601) Iteration limit reached at time 10 ns.
# ** Note: (vsim-3602) Delays were truncated during elaboration of the
design.