Hi everyone! I'm writing a vhdl code for the system in attachment. I have no error when I compile the code but I have an error when I elaborate. ncelab: *E,CSGMSS: multiple sources for unresolved signal: INT1 [188.8.131.52]. Computing driving value: :systeme_comparateur_tb(archi):uut@systeme_c omparateur(archi):int1 In port map at: ../sources/systeme_comparateur_arch.vhdl, line: 95, position: 34 This is my code below:
library ieee; use ieee.std_logic_1164.all; library analogdevice_lib; use analogdevice_lib.all; library st_lib; use st_lib.all; entity systeme_comparateur is port(enable_mux4_comp1, enable_mux8_comp1, enable_mux4_comp2, enable_mux8_comp2 : in std_logic; A_mux4_comp1, A_mux4_comp2 : in std_logic_vector (1 downto 0); A_mux8_comp1, A_mux8_comp2 : in std_logic_vector (2 downto 0); S_mux4_comp1, S_mux4_comp2 : in real_vector (3 downto 0); S_mux8_comp1, S_mux8_comp2 : in real_vector (7 downto 0); In_switch : in std_logic; Sortie_comp1, Sortie_comp2 : out real); end systeme_comparateur; architecture archi of systeme_comparateur is component analog_ADG704 generic (INPUTS_SEL: integer); port(EN : in std_logic; A : in std_logic_vector (INPUTS_SEL-1 downto 0); S : in real_vector (2**INPUTS_SEL-1 downto 0); D : out real); end component; component analog_ADG708 generic (INPUTS_SEL: integer); port(EN : in std_logic; A : in std_logic_vector (INPUTS_SEL-1 downto 0); S : in real_vector (2**INPUTS_SEL-1 downto 0); D : out real); end component; component analog_comparateur generic (vcc : real; gnd : real); port(in_pos : in real; in_neg : in real; s_comp : out real); end component; component analog_ADG712_1 port(In_ADG_1: in std_logic; D_ADG_1: in real; S_ADG_1: out real); end component; signal int1, int2, int3, int4 : real; begin mux4_comp1: analog_ADG704 generic map (INPUTS_SEL => 2) port map (enable_mux4_comp1, A_mux4_comp1, S_mux4_comp1, int1); mux8_comp1: analog_ADG708 generic map (INPUTS_SEL => 3) port map (enable_mux8_comp1, A_mux8_comp1, S_mux8_comp1, int2); comp1: analog_comparateur generic map (vcc => 5.0, gnd => 0.0) port map (int1, int2, Sortie_comp1); mux4_comp2: analog_ADG704 generic map (INPUTS_SEL => 2) port map (enable_mux4_comp2, A_mux4_comp2, S_mux4_comp2, int3); mux8_comp2: analog_ADG708 generic map (INPUTS_SEL => 3) port map (enable_mux8_comp2, A_mux8_comp2, S_mux8_comp2, int4); comp2: analog_comparateur generic map (vcc => 5.0, gnd => 0.0) port map (int3, int4, Sortie_comp2); switch: analog_ADG712_1 port map (In_switch, int3, int1); end archi;
With this code, I can't run a simulation. So I think I'm wrong when I connect the ports of ADG712 component with the rest of the system. Could you help me please ?
mux4_comp1: analog_ADG704 generic map (INPUTS_SEL => 2) port map (enable_mux4_comp1, A_mux4_comp1, S_mux4_comp1, int1); .... switch: analog_ADG712_1 port map (In_switch, int3, int1); int1 is used as out signal from 2 components?
I use int1 signal to modelise the wire between ADG704 (U127) output and TS3021ILT (U126) positive input. So, if you get a look on the schema, there is the port '3' of ADG712 (U152A) which is also connected on this wire. I don't know if it's correct...
not. as far as I know.
Any idea to code that?? If it's possible^^
I think, you have to create a new components, which takes two inputs (both int1) and creates one resulting signal. You have to specify the best way how to combine both signals(and, or , sum, select). It depends on your goals.
agathepower wrote: > component analog_ADG704 > generic (INPUTS_SEL: integer); > port(EN : in std_logic; > A : in std_logic_vector (INPUTS_SEL-1 downto 0); > S : in real_vector (2**INPUTS_SEL-1 downto 0); > D : out real); > > component analog_ADG712_1 > port(In_ADG_1: in std_logic; > D_ADG_1: in real; > S_ADG_1: out real); The models of the switches are wrong. According to the datasheet, all of the S are inout and also D is inout. How do the models reflect the state "switch off"/"all switches off" to the d output? Is there a 'Z' level possible on the output (as it will be in reality)? How do you resolve the conflict when one switch drives 'Z' and another switch drives "3.3" on the same wire? All in all you cann say: the VHDL description is not equal to the schematic, because in a switch both terminals are inout and a switch can be high-Z (just "open"). All in all I would say that you will need a special type for the "analog" signals. You need a type thats possible to reflect the high-Z value of an open switch. So have a look at this switch model (google translate will help out): http://www.lothar-miller.de/s9y/archives/91-Schalter-und-Bruecke.html Maybe it gives you a hint how to build such a switch.
: Edited by Moderator
Hi and thank you for your answer! Lothar Miller wrote: > The models of the switches are wrong. According to the datasheet, all of > the S are inout and also D is inout. I know, in fact the code in your link is working with std_logic but not with real. I already tested that. With real the error "multiple sources for unresolved signal" occurs in elaboration. To pass through this issue I modelise only D to S, that why I have D:in and S:out in my code, because according to my tutor in this system there is only one possible sens. If we imagine that not a ADG712 component but just a switch with an input, an output, and a command signal, how can I connect these ports with the rest of the system without error? I put the schemas in attachment
agathepower wrote: > If we imagine that not a ADG712 component but just a switch with an > input, an output, and a command signal, how can I connect these ports > with the rest of the system without error? You can't implement a switch for real numbers. Just try to tell me: what would be on the output of this switch, if the input is 1.11 and the switch is on? And what would be the output when the switch is switched off? Why isn't it possible to handle this second case with a real value? The only possibility you have is to implement a 2:1 multiplexer. That can be done with a real number. And the input of that mux is either the output of the lower mux and the output of the upper opamp in your sketches... BTW: I scaled down your images size by a factor of 30 without any loss of information.
: Edited by Moderator
Lothar Miller wrote: > The only possibility you have is to implement a 2:1 multiplexer Thank you, I think that is the right solution. Nothing to do with it, but I have an other question. Is it possible to connect an internal signal to a "bit" of a vector (not a bit but I don't know how to say it with "real") ? In fact I want to connect signals generator on each S inputs of each mux. I have already the signal generator, it's an entity with no input and one output, this output is connected to an internal signal and this signal is connected to a "bit" of S vector on each mux. I don't know if I'm clear... Thank you for your help