hey, guys! can you help me with part of veilog code? always@(posedge clk) begin if(counter<=width) out <=1'b1; else out <=1'b0; counter<=counter+1'd1; if(counter>=18'd195312) counter=18'b0; $display("%d",counter[17:0]); end when COUNTER equals 195312 I want set to null it. it nulled, but the next clock CLK continues to count COUNTER to 195313... why is this happening???
You have used both non-blocking and blocking assignmemnts to counter.
you could have used correct indentation (with the [ code ] [ /code ] tags to make clear what happens in your code... And, is this to complete code?
berndl wrote: > And, is this to complete > code? argh, should read: And, is this the complete code?