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Forum: FPGA, VHDL & Verilog How to increases Maximum operating freqency


von Vinayak S. (vinayak_s)


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1
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity map1 is
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  port(clk:in std_logic;
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  reset:in std_logic;
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  code_rate:in std_logic_vector(3 downto 0);
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  mod_mode_sel:in std_logic_vector(1 downto 0);
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  N_ldpc:in std_logic_vector(15 downto 0);
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  input1:in std_logic;
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  out_R:out std_logic_vector(15 downto 0);
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  out_I:out std_logic_vector(15 downto 0));
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end map1;
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architecture arch of map1 is
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subtype select_1_2 is integer;
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type select_e is array (0 to 2, 0 to 63) of select_1_2;
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constant e:select_e:= ((7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 15,1,13,3,8,11,9,5,10,6,4,7,12,2,14,0, 7,3,1,5,2,6,4,0) , (0,5,1,2,4,7,3,6, 7,1,4,2,5,3,6,0, 2,7,6,9,0,3,1,8,4,11,5,10, 11,7,3,10,6,2,9,5,1,8,4,0, 2,11,3,4,0,9,1,8,10,13,7,14,6,15,5,12, 7,3,1,5,2,6,4,0) , (7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 7,2,9,0,4,6,13,3,14,10,15,5,8,12,11,1,  7,3,1,5,2,6,4,0));
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type select_16 is array (0 to 3) of std_logic_vector(15 downto 0);
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signal Zq_16:select_16:= ("0011110010110111", "0001010000111101", "1011110010110111", "1001010000111101"); 
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type select_64 is array (0 to 7) of std_logic_vector(15 downto 0);
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constant Zq_64:select_64:= ("0100010100100000", "0011000101100000", "0000100111100000", "0011001101010000", "1100010100100000", "1011000101100000", "1000100111100000", "1011001101010000");
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type select_256 is array (0 to 15) of std_logic_vector(15 downto 0);
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constant Zq_256:select_256:= ("0100100110100000", "0011111111001111", "0010110000101101", "0011010111111110", "0000010011101000", "0000111010111001", "0010001001011100", "0001100010001010", "1100100110100000", "1011111111001111", "1010110000101101", "1011010111111110", "1000010011101000", "1000111010111001", "1010001001011100", "1001100010001010");
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signal rate : integer range 0 to 4;
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signal mod_sel : integer range 0 to 63;
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signal SET : integer range 0 to 16;
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signal b: std_logic_vector(31 downto 0);
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signal count: integer range 0 to 33;
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signal flag : std_logic;
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begin
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  flag <= '0' when reset = '1' else '1' when  count = SET+SET ;
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  ---here "0001" is for code rate 3/5 , "0010" for code rate 2/3 and "0000" for all others....
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  rate <= 0 when code_rate ="0000"  else 1 when code_rate = "0001" else 2 when code_rate = "0010" else 0 ;
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  ---depending on the modulation format and N_ldpc value index going to change--------
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  mod_sel <= 0  when (mod_mode_sel = "01" and N_ldpc="1111110100100000") else
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             8  when (mod_mode_sel = "01" and N_ldpc="0011111101001000") else
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             16 when (mod_mode_sel = "10" and N_ldpc="1111110100100000") else
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             28 when (mod_mode_sel = "10" and N_ldpc="0011111101001000") else
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             40 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else
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             56 when (mod_mode_sel = "11" and N_ldpc="0011111101001000") ;
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  ---- selecting number of substreams--------------          
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  SET <= 2  when mod_mode_sel = "00"  else
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         8  when mod_mode_sel = "01"  else 
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         12 when mod_mode_sel = "10" else 
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         16 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else 
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         8  when (mod_mode_sel = "11" and N_ldpc="0011111101001000");
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process(clk, reset)
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  begin
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    if reset = '1' then
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      count <= 0;
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    elsif rising_edge(clk) then
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      if count = SET+SET then
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        count <= 1;
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      else 
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        count <= count + 1;
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      end if;
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    end if;
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end process;
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process(clk, reset , flag)
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  variable i: integer ;
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  variable j: integer ;
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  begin
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    if reset = '1' then
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     b <= (others=>'0'); 
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     i := 0; 
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     j := 0;
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    elsif rising_edge(clk) then
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      if  (mod_mode_sel /= "00" and (count >= 1 and count <= SET+SET)) then 
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        b( e(rate , mod_sel+i) + j ) <= input1;
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          i := i + 1 ;
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            if i = SET then
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              j :=  j + SET ;
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              i := 0 ;
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            end if;
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            if j = SET+SET then
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              j := 0 ;
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            end if;
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      end if;
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  end if;
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end process;
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process (clk)
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  variable sel_1: std_logic_vector(3 downto 0);
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  variable sel_2: std_logic_vector(3 downto 0);
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  begin
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    if rising_edge(clk) then
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      ------Mapping for QPSK----------
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      if mod_mode_sel = "00" and count >= 1 then
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        if input1 = '0' then
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          out_r <= "0101101010000010" ;
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          out_i <= "0101101010000010" ;
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        elsif input1 ='1' then
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          out_r <= "1101101010000010" ;
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          out_i <= "1101101010000010" ;
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        end if;
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      end if;
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      -------Mapping for both 16-QAM ,64800/16200  and 256-QAM , 16200 ---------
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     if mod_mode_sel = "01" or (mod_mode_sel = "11" and N_ldpc="0011111101001000") then  
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      if  count = 9 then 
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          sel_1 := "00" & b(0) & b(2) ;
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          out_r <= Zq_16(to_integer(unsigned(sel_1)));
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          sel_2 := "00" & b(1) & b(3) ;
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          out_i <= Zq_16(to_integer(unsigned(sel_2)));
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      end if; 
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      if  count = 13 then 
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          sel_1 := "00" & b(4) & b(6) ;
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          out_r <= Zq_16(to_integer(unsigned(sel_1)));
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          sel_2 := "00" & b(5) & b(7) ;
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          out_i <= Zq_16(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 1 then 
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          sel_1 := "00" & b(8) & b(10) ;
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          out_r <= Zq_16(to_integer(unsigned(sel_1))); 
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          sel_2 := "00" & b(9) & b(11) ;
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          out_i <= Zq_16(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 5 then 
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          sel_1 := "00" & b(12) & b(14) ;
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          out_r <= Zq_16(to_integer(unsigned(sel_1)));
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          sel_2 := "00" & b(13) & b(15) ;
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          out_i <= Zq_16(to_integer(unsigned(sel_2)));
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      end if;
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    end if;
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    -------Mapping for 64-QAM and 64800/16200---------
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    if mod_mode_sel = "10"   then        
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      if  count = 13 then 
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          sel_1 := '0' & b(0) & b(2) & b(4) ;
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          out_r <= Zq_64(to_integer(unsigned(sel_1)));
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          sel_2 := '0' & b(1) & b(3) & b(5) ;
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          out_i <= Zq_64(to_integer(unsigned(sel_2)));
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      end if;
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      if  count = 19 then 
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          sel_1 := '0' & b(6) & b(8) & b(10) ;
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          out_r <= Zq_64(to_integer(unsigned(sel_1)));
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          sel_2 := '0' & b(7) & b(9) & b(11) ;
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          out_i <= Zq_64(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 1 then 
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          sel_1 := '0' & b(12) & b(14) & b(16) ;
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          out_r <= Zq_64(to_integer(unsigned(sel_1))); 
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          sel_2 := '0' & b(13) & b(15) & b(17) ;
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          out_i <= Zq_64(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 7 then 
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          sel_1 := '0' & b(18) & b(20) & b(22) ;
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          out_r <= Zq_64(to_integer(unsigned(sel_1))); 
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          sel_2 := '0' & b(19) & b(21) & b(23) ;
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          out_i <= Zq_64(to_integer(unsigned(sel_2)));
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      end if;
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 end if; 
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   -------Mapping for 256-QAM and 64800---------
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   if (mod_mode_sel = "11" and N_ldpc="1111110100100000")  then        
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      if  count = 17 then 
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          sel_1 := b(0) & b(2) & b(4) & b(6) ;
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          out_r <= Zq_256(to_integer(unsigned(sel_1))); 
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          sel_2 := b(1) & b(3) & b(5) & b(7) ;
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          out_i <= Zq_256(to_integer(unsigned(sel_2)));
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      end if;
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      if  count = 25 then 
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          sel_1 := b(8) & b(10) & b(12) & b(14) ;
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          out_r <= Zq_256(to_integer(unsigned(sel_1)));
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          sel_2 := b(9) & b(11) & b(13) & b(15) ;
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          out_i <= Zq_256(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 1 then 
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          sel_1 := b(16) & b(18) & b(20) & b(22) ;
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          out_r <= Zq_256(to_integer(unsigned(sel_1)));
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          sel_2 := b(17) & b(19) & b(21) & b(23) ;
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          out_i <= Zq_256(to_integer(unsigned(sel_2)));
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      end if;
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      if flag = '1' and  count = 9 then 
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          sel_1 := b(24) & b(26) & b(28) & b(30) ;
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          out_r <= Zq_256(to_integer(unsigned(sel_1)));
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          sel_2 := b(25) & b(27) & b(29) & b(31) ;
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          out_i <= Zq_256(to_integer(unsigned(sel_2)));
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      end if;
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 end if;
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 end if;
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  end process;
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end arch;

when I synthesized its give 87MHz in Spartan 3A-DSP.

pls help me......

: Edited by Moderator
von Schlumpf (Guest)


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google: "pipelining"

von Duke Scarring (Guest)


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At first you should use [ vhdl ] and [ / vhdl ] to tag the code (use 
tags without spaces).

Second, to enhance readability I would suggest
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out_r <= std_lgoic_vector( to_unsigned( 23170, 16));
rather than
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out_r <= "0101101010000010" ;
To define out_r as unsigned could further enhance clarity.

Vinayak S. wrote:
> when I synthesized its give 87MHz in Spartan 3A-DSP.
What speed did you need?
The 87 MHz, is then number from synthesis only or after place & route?

Duke

von Lothar M. (lkmiller) (Moderator)


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Duke Scarring wrote:
> At first you should use [ vhdl ] and [ / vhdl ] to tag the code
I did it and got a little magic: syntax highlighting.

Vinayak S. wrote:
1
 subtype select_1_2 is integer;
Why this? A subtype is useful if you want to constrain the base type. 
Somthing like this:
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 subtype select_1_2 is integer range 0 to 12;

> b( e(rate , mod_sel+i) + j ) <= input1;
Do you know that this is a big monstermultiplexer. Maybe you can 
implement this function with a RAM. That would be much faster...

> when I synthesized its give 87MHz in Spartan 3A-DSP.
Fine. And whats the problem with that? Which one is the critical path?

: Edited by Moderator

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