1 | library ieee ; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | |
5 | entity map1 is |
6 | port(clk:in std_logic; |
7 | reset:in std_logic; |
8 | code_rate:in std_logic_vector(3 downto 0); |
9 | mod_mode_sel:in std_logic_vector(1 downto 0); |
10 | N_ldpc:in std_logic_vector(15 downto 0); |
11 | input1:in std_logic; |
12 | out_R:out std_logic_vector(15 downto 0); |
13 | out_I:out std_logic_vector(15 downto 0)); |
14 | end map1; |
15 | |
16 | architecture arch of map1 is |
17 | |
18 | |
19 | subtype select_1_2 is integer; |
20 | type select_e is array (0 to 2, 0 to 63) of select_1_2; |
21 | constant e:select_e:= ((7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 15,1,13,3,8,11,9,5,10,6,4,7,12,2,14,0, 7,3,1,5,2,6,4,0) , (0,5,1,2,4,7,3,6, 7,1,4,2,5,3,6,0, 2,7,6,9,0,3,1,8,4,11,5,10, 11,7,3,10,6,2,9,5,1,8,4,0, 2,11,3,4,0,9,1,8,10,13,7,14,6,15,5,12, 7,3,1,5,2,6,4,0) , (7,1,4,2,5,3,6,0, 7,1,4,2,5,3,6,0, 11,7,3,10,6,2,9,5,1,8,4,0, 11,7,3,10,6,2,9,5,1,8,4,0, 7,2,9,0,4,6,13,3,14,10,15,5,8,12,11,1, 7,3,1,5,2,6,4,0)); |
22 | |
23 | type select_16 is array (0 to 3) of std_logic_vector(15 downto 0); |
24 | signal Zq_16:select_16:= ("0011110010110111", "0001010000111101", "1011110010110111", "1001010000111101"); |
25 | |
26 | type select_64 is array (0 to 7) of std_logic_vector(15 downto 0); |
27 | constant Zq_64:select_64:= ("0100010100100000", "0011000101100000", "0000100111100000", "0011001101010000", "1100010100100000", "1011000101100000", "1000100111100000", "1011001101010000"); |
28 | |
29 | type select_256 is array (0 to 15) of std_logic_vector(15 downto 0); |
30 | constant Zq_256:select_256:= ("0100100110100000", "0011111111001111", "0010110000101101", "0011010111111110", "0000010011101000", "0000111010111001", "0010001001011100", "0001100010001010", "1100100110100000", "1011111111001111", "1010110000101101", "1011010111111110", "1000010011101000", "1000111010111001", "1010001001011100", "1001100010001010"); |
31 | |
32 | signal rate : integer range 0 to 4; |
33 | signal mod_sel : integer range 0 to 63; |
34 | signal SET : integer range 0 to 16; |
35 | signal b: std_logic_vector(31 downto 0); |
36 | signal count: integer range 0 to 33; |
37 | signal flag : std_logic; |
38 | |
39 | begin
|
40 | |
41 | |
42 | flag <= '0' when reset = '1' else '1' when count = SET+SET ; |
43 | |
44 | ---here "0001" is for code rate 3/5 , "0010" for code rate 2/3 and "0000" for all others....
|
45 | |
46 | rate <= 0 when code_rate ="0000" else 1 when code_rate = "0001" else 2 when code_rate = "0010" else 0 ; |
47 | |
48 | ---depending on the modulation format and N_ldpc value index going to change--------
|
49 | mod_sel <= 0 when (mod_mode_sel = "01" and N_ldpc="1111110100100000") else |
50 | 8 when (mod_mode_sel = "01" and N_ldpc="0011111101001000") else |
51 | 16 when (mod_mode_sel = "10" and N_ldpc="1111110100100000") else |
52 | 28 when (mod_mode_sel = "10" and N_ldpc="0011111101001000") else |
53 | 40 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else |
54 | 56 when (mod_mode_sel = "11" and N_ldpc="0011111101001000") ; |
55 | |
56 | ---- selecting number of substreams--------------
|
57 | SET <= 2 when mod_mode_sel = "00" else |
58 | 8 when mod_mode_sel = "01" else |
59 | 12 when mod_mode_sel = "10" else |
60 | 16 when (mod_mode_sel = "11" and N_ldpc="1111110100100000") else |
61 | 8 when (mod_mode_sel = "11" and N_ldpc="0011111101001000"); |
62 | |
63 | process(clk, reset) |
64 | begin
|
65 | if reset = '1' then |
66 | count <= 0; |
67 | |
68 | elsif rising_edge(clk) then |
69 | if count = SET+SET then |
70 | count <= 1; |
71 | else
|
72 | count <= count + 1; |
73 | end if; |
74 | end if; |
75 | end process; |
76 | |
77 | process(clk, reset , flag) |
78 | variable i: integer ; |
79 | variable j: integer ; |
80 | |
81 | begin
|
82 | |
83 | if reset = '1' then |
84 | b <= (others=>'0'); |
85 | i := 0; |
86 | j := 0; |
87 | |
88 | elsif rising_edge(clk) then |
89 | |
90 | if (mod_mode_sel /= "00" and (count >= 1 and count <= SET+SET)) then |
91 | |
92 | b( e(rate , mod_sel+i) + j ) <= input1; |
93 | i := i + 1 ; |
94 | |
95 | |
96 | if i = SET then |
97 | j := j + SET ; |
98 | i := 0 ; |
99 | end if; |
100 | |
101 | if j = SET+SET then |
102 | j := 0 ; |
103 | end if; |
104 | |
105 | |
106 | end if; |
107 | end if; |
108 | end process; |
109 | |
110 | |
111 | process (clk) |
112 | variable sel_1: std_logic_vector(3 downto 0); |
113 | variable sel_2: std_logic_vector(3 downto 0); |
114 | |
115 | begin
|
116 | if rising_edge(clk) then |
117 | |
118 | ------Mapping for QPSK----------
|
119 | |
120 | if mod_mode_sel = "00" and count >= 1 then |
121 | if input1 = '0' then |
122 | out_r <= "0101101010000010" ; |
123 | out_i <= "0101101010000010" ; |
124 | elsif input1 ='1' then |
125 | out_r <= "1101101010000010" ; |
126 | out_i <= "1101101010000010" ; |
127 | end if; |
128 | end if; |
129 | |
130 | -------Mapping for both 16-QAM ,64800/16200 and 256-QAM , 16200 ---------
|
131 | if mod_mode_sel = "01" or (mod_mode_sel = "11" and N_ldpc="0011111101001000") then |
132 | |
133 | if count = 9 then |
134 | |
135 | sel_1 := "00" & b(0) & b(2) ; |
136 | out_r <= Zq_16(to_integer(unsigned(sel_1))); |
137 | |
138 | sel_2 := "00" & b(1) & b(3) ; |
139 | out_i <= Zq_16(to_integer(unsigned(sel_2))); |
140 | |
141 | end if; |
142 | |
143 | if count = 13 then |
144 | |
145 | sel_1 := "00" & b(4) & b(6) ; |
146 | out_r <= Zq_16(to_integer(unsigned(sel_1))); |
147 | |
148 | sel_2 := "00" & b(5) & b(7) ; |
149 | out_i <= Zq_16(to_integer(unsigned(sel_2))); |
150 | end if; |
151 | |
152 | if flag = '1' and count = 1 then |
153 | |
154 | sel_1 := "00" & b(8) & b(10) ; |
155 | out_r <= Zq_16(to_integer(unsigned(sel_1))); |
156 | |
157 | sel_2 := "00" & b(9) & b(11) ; |
158 | out_i <= Zq_16(to_integer(unsigned(sel_2))); |
159 | end if; |
160 | |
161 | if flag = '1' and count = 5 then |
162 | |
163 | sel_1 := "00" & b(12) & b(14) ; |
164 | out_r <= Zq_16(to_integer(unsigned(sel_1))); |
165 | |
166 | sel_2 := "00" & b(13) & b(15) ; |
167 | out_i <= Zq_16(to_integer(unsigned(sel_2))); |
168 | end if; |
169 | end if; |
170 | |
171 | -------Mapping for 64-QAM and 64800/16200---------
|
172 | |
173 | if mod_mode_sel = "10" then |
174 | if count = 13 then |
175 | |
176 | sel_1 := '0' & b(0) & b(2) & b(4) ; |
177 | out_r <= Zq_64(to_integer(unsigned(sel_1))); |
178 | |
179 | sel_2 := '0' & b(1) & b(3) & b(5) ; |
180 | out_i <= Zq_64(to_integer(unsigned(sel_2))); |
181 | end if; |
182 | |
183 | if count = 19 then |
184 | |
185 | sel_1 := '0' & b(6) & b(8) & b(10) ; |
186 | out_r <= Zq_64(to_integer(unsigned(sel_1))); |
187 | |
188 | sel_2 := '0' & b(7) & b(9) & b(11) ; |
189 | out_i <= Zq_64(to_integer(unsigned(sel_2))); |
190 | end if; |
191 | |
192 | if flag = '1' and count = 1 then |
193 | |
194 | sel_1 := '0' & b(12) & b(14) & b(16) ; |
195 | out_r <= Zq_64(to_integer(unsigned(sel_1))); |
196 | |
197 | sel_2 := '0' & b(13) & b(15) & b(17) ; |
198 | out_i <= Zq_64(to_integer(unsigned(sel_2))); |
199 | end if; |
200 | |
201 | if flag = '1' and count = 7 then |
202 | |
203 | sel_1 := '0' & b(18) & b(20) & b(22) ; |
204 | out_r <= Zq_64(to_integer(unsigned(sel_1))); |
205 | |
206 | sel_2 := '0' & b(19) & b(21) & b(23) ; |
207 | out_i <= Zq_64(to_integer(unsigned(sel_2))); |
208 | end if; |
209 | |
210 | end if; |
211 | |
212 | -------Mapping for 256-QAM and 64800---------
|
213 | |
214 | if (mod_mode_sel = "11" and N_ldpc="1111110100100000") then |
215 | if count = 17 then |
216 | |
217 | sel_1 := b(0) & b(2) & b(4) & b(6) ; |
218 | out_r <= Zq_256(to_integer(unsigned(sel_1))); |
219 | |
220 | sel_2 := b(1) & b(3) & b(5) & b(7) ; |
221 | out_i <= Zq_256(to_integer(unsigned(sel_2))); |
222 | end if; |
223 | |
224 | if count = 25 then |
225 | |
226 | sel_1 := b(8) & b(10) & b(12) & b(14) ; |
227 | out_r <= Zq_256(to_integer(unsigned(sel_1))); |
228 | |
229 | sel_2 := b(9) & b(11) & b(13) & b(15) ; |
230 | out_i <= Zq_256(to_integer(unsigned(sel_2))); |
231 | end if; |
232 | |
233 | if flag = '1' and count = 1 then |
234 | |
235 | sel_1 := b(16) & b(18) & b(20) & b(22) ; |
236 | out_r <= Zq_256(to_integer(unsigned(sel_1))); |
237 | |
238 | sel_2 := b(17) & b(19) & b(21) & b(23) ; |
239 | out_i <= Zq_256(to_integer(unsigned(sel_2))); |
240 | end if; |
241 | |
242 | if flag = '1' and count = 9 then |
243 | |
244 | sel_1 := b(24) & b(26) & b(28) & b(30) ; |
245 | out_r <= Zq_256(to_integer(unsigned(sel_1))); |
246 | |
247 | sel_2 := b(25) & b(27) & b(29) & b(31) ; |
248 | out_i <= Zq_256(to_integer(unsigned(sel_2))); |
249 | end if; |
250 | |
251 | end if; |
252 | end if; |
253 | |
254 | end process; |
255 | |
256 | end arch; |
when I synthesized its give 87MHz in Spartan 3A-DSP. pls help me......