Vinayak S. wrote:
> I design using signal and variables in VHDL which is not
> synthesizing....
> help me what best way of implimentation....

Do you really think it is a good idea to start learning VHDL with a 
project like this?

I'm doing internship in company and they give me project like this. And 
more over i need to submit project for my PG..

so, i started well but i stuck at here pls guide me how to implement 
i'll do my best..

You do internship and there is nobody guiding you a little bit?

Well, you have to implement one ore more shift registers and a control 
logic.
If it is not synthesizing it is not a matter of the usage of signals and 
variables. You asked this in another post and got a answers where the 
problem might be.

Vinayak S. wrote:
> I'm doing internship in company and they give me project like this. And
> more over i need to submit project for my PG..
>
> so, i started well but i stuck at here pls guide me how to implement
> i'll do my best..

This begs the question what is the task you have been given:
Complete DVB-T2 modulator or demodulator or just parts like the 
interleaver?

Vinayak S. wrote:
> complete DVB-T2 modulator....

Vinayak S. wrote:
> I design using signal and variables in VHDL which is not
> synthesizing....

Vinayak S. wrote:
> internship

I think you are not very familiar with FPGA and HDL and digital design.
Is that right?
If yes, what kind of help do you expect? Complete source code? A couple 
of hints how to start with the problem?

If you are a beginner in VHDL you will fail to implement a DVB-T2 
modulator within an internship.

Hello,
first of all if you want to implement only the 16-Qam with 64800_BITS 
then you need exactly 4050_Bytes so your RAM should have a size of 
4096_Bytes or 32768_BITS.
But also if YOU want to implement a ""complete" DVB-T2 whatever" this 
will be an easy Task compared to other Sections.
And if you still want to implement this then my Tipp is use an ram two 
counters and a State-Machine to control the flow, the Diagramm already 
shows you how.

To my mind, one should distinguish the subsequent issues:

1) Learning Digital Design and Digital Behavior
2) Learning Implementation of logic fuctions in digital domains
3) Learning VHDL to realize the ideas
4) Learning about the particular task

I see demand in all those aspects so I second the sencence above that 
this task is no good for beginning.

Anyway one should at least be able to write down a step be step task 
list, what the interleaver should do at any point of time, where data is 
obtained from and moved to, and what treatment is applied. Graphical 
diagrams will help to express people's thougths and indicate any 
misunderstandings to people in the forum.

Also I have to point out that it is no good to ask silently here in the 
forum. Ask the one who gave you the task, so that he has a feed back 
about your knowledge. If you do no do this, he will continue to 
verestimate your abilities and overload you with work.