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Forum: FPGA, VHDL & Verilog state machine in vhdl


von Basma H. (Company: bhit) (basma)


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hi all,

i need to execute this state machine?
state machine of s0,s1,s2
s0: read ram1(address at 0) into ram1_data register, one clock,move to 
s1
s1:read ram2(address 0~till equality) into ram2 register, several 
clocks, if equality found between ram1/ram2 data set ram2 address
to zero, output (address difference), move to s2
s2:set ram1 address to 1(increment),one clock, move to s0
start again for ram1 address 1 and so on.
 i tried but it failed,
please ,any help ???
1
library ieee;
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use ieee.std_logic_1164.all;
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entity test is
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    port(
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        rst      : in  std_logic;
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        clk      : in  std_logic;
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        we       : in  std_logic;
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        wr_data1 : in  std_logic_vector(7 downto 0);
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        wr_data2 : in  std_logic_vector(7 downto 0);
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        wr_addr  : in  integer range 0 to 255;
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        distance : out integer range 0 to 255;
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        vout     : out std_logic;
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        no_match : out std_logic
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         );
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end entity;
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architecture rtl of test is
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signal rd_data1 : std_logic_vector(7 downto 0);
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signal rd_data2 : std_logic_vector(7 downto 0);
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signal rd_addr1 : integer range 0 to 255 := 0;
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signal rd_addr2 : integer range 0 to 255 := 0;
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type states is (s0,s1,s2);
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signal state: states;
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component wr_rd_ram
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    port(
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        clk      : in  std_logic;
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        we       : in  std_logic;
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        wr_data  : in  std_logic_vector(7 downto 0);
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        wr_addr  : in  integer range 0 to 255;
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        rd_addr  : in  integer range 0 to 255; 
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        rd_data  : out std_logic_vector(7 downto 0)
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         );
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end component;
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begin
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ram1:wr_rd_ram
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    port map(
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        clk      => clk,
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        we       => we,
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        wr_data  => wr_data1,
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        wr_addr  => wr_addr,
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        rd_addr  => rd_addr1, 
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        rd_data  => rd_data1
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         );
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ram2:wr_rd_ram
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    port map(
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        clk      => clk,
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        we       => we,
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        wr_data  => wr_data2,
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        wr_addr  => wr_addr,
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        rd_addr  => rd_addr2, 
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        rd_data  => rd_data2
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         );
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----state machine 
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process(rst,clk)
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begin
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if rst = '1' then
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    state <= s0;
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    vout <= '0';
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    no_match <= '0';
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    distance <= 0;
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elsif rising_edge(clk) then
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   vout <= '0';
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   no_match <= '0';
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   case state is
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      when s0 =>
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        rd_addr2 <= rd_addr2 + 1;
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        if rd_data1 = rd_data2 then
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           state <= s1;
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           distance <= rd_addr1 - rd_addr2;
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           vout <= '1';
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        elsif rd_addr2 = 255 then
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           rd_addr2 <= 0;
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           state <= s2;
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        end if;
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      when s1 =>
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        rd_addr1 <= rd_addr1 + 1;
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        rd_addr2 <= 0;
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        state <= s0;
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      when s2 => 
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         no_match <= '1';
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         state <= s0;
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      when others => null;
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   end case;
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end if;
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end process;
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end rtl;

: Edited by Moderator
von Innensechskant (Guest)


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Please try to be more specific about the issue.
What are the symptoms, the error messages or warnings which give you the 
impression that there is a failure?

von Basma H. (Company: bhit) (basma)


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the problem with state machine didn't gave me the correct result
1
----state machine
2
process(rst,clk)
3
begin
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if rst = '1' then
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    state <= s0;
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    vout <= '0';
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    no_match <= '0';
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    distance <= 0;
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elsif rising_edge(clk) then
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   vout <= '0';
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   no_match <= '0';
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   case state is
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      when s0 =>
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        rd_addr2 <= rd_addr2 + 1;
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        if rd_data1 = rd_data2 then
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           state <= s1;
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           distance <= rd_addr1 - rd_addr2;
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           vout <= '1';
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        elsif rd_addr2 = 255 then
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           rd_addr2 <= 0;
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           state <= s2;
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        end if;
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      when s1 =>
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        rd_addr1 <= rd_addr1 + 1;
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        rd_addr2 <= 0;
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        state <= s0;
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      when s2 =>
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         no_match <= '1';
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         state <= s0;
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      when others => null;
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   end case;
38
end if;
39
end process;
40
41
end rtl;

: Edited by Moderator
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Basma Hassan wrote:
> the problem with state machine didn't gave me the correct result
How did you find that out? With a simulation? What do you expect? And 
what do you get? Are your RAMs working as expexted?
Pls. supply as much information as possible, its not funny to beg and 
plead for each piece of information... :-/

BTW: use the tokens [ vhdl ] and [ /vhdl ] (without the whitespaces) 
around your VHDL code. Then syntax highlighting makes reading much 
easier!

: Edited by Moderator
von Basma H. (Company: bhit) (basma)


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> How did you find that out? With a simulation? What do you expect? And
> what do you get? Are your RAMs working as expected?

i use xilinx 9.2i simulator ,we want to produce an array containing the 
distances from each element in memory1 to the element holding the same 
value in memory2. I.e searching for similarity, RAMs are worked well 
,the state machine is synthesize.i put my code previous assuming each 
element in the memory is std_logic_vector(0 to 7), and addresses from 0 
to 255.if the element in mem1 is 00010100 has address 2 & the same 
element in the mem2 has the address 10 the addresses difference(2-10)=8 
is the distance and so on.
i hope you understand me.thanks a lot.

: Edited by User
von dden (Guest)


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Lol, maybe you take a look at rd_addr2 and think again, its obvious when 
you simulate this, because rd_addr2 will never change and also maybe you 
also hang forever in s0.


Mfg

von Pete (Guest)


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Hmm why should rd_addr2 never change?

von Basma H. (Company: bhit) (basma)


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>its obvious when
> you simulate this, because rd_addr2 will never change and also maybe you
> also hang forever in s0
you mean the line rd_addr2=255;

von Pete (Guest)


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Hey Basama
Please tell us what failed. How did you tested? What was the outcome, 
output?

von Basma H. (Company: bhit) (basma)


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> Hey Basama
> Please tell us what failed. How did you tested? What was the outcome,
> output?

when i simulate the previous code the output distance always=0
i expected it to be such as 1+6+9+1+7+..... the distance between every 
element in mem1 and the same element in mem2.

von Pete (Guest)


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For me, your code seems to work. Maybe it's a problem with your 
simulation. Can you post the testbench?

von dden (Guest)


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you define for rd_addr1/2 an integer range 0 to 255 and then you 
calculate
 for example 0-1=?? if the data match, im sure your simulator gives a 
warning about this.

von basma (Guest)


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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?
i simulate without testbench
i smulate using testbench waveform

von dden (Guest)


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Hi,
and how did you test it using testbench waveform??
Should it look like the ones I attached?
There are also some incomplete Descriptions but it should "work", just 
make the changes I suggested.

For what do you design this?


Mfg

von basma (Guest)


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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?
hi,
the design is acts very well the problem if you see the picture attached 
is if rd_data1=rd_data2 then
rd_addr2 =0 but rd_data2 count the next element then start from 0 it 
make shift in rd_data2 and therefore count  false distance.
i want to do if data1=data2 then start from begining rd_data=0 and 
rd_data2=0 . i hope you understand me

von basma (Guest)


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then i want to sumation the all distance value .

von dden (Guest)


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Hi,
well then your problem is that you count every s0-State, even if 
rd1=rd2.
Try something like this:
1
      when s0 =>
2
        if rd_data1 = rd_data2 then
3
           state <= s1;
4
           distance <= rd_addr1 - rd_addr2;
5
           vout <= '1';
6
        elsif rd_addr2 = 255 then
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           rd_addr2 <= 0;
8
           state <= s2;
9
        else
10
           rd_addr2 <= rd_addr2 + 1;
11
        end if;

von basma (Guest)


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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?

dden wrote:
> Hi,
> well then your problem is that you count every s0-State, even if
> rd1=rd2.
> Try something like this:      when s0 =>
>         if rd_data1 = rd_data2 then
>            state <= s1;
>            distance <= rd_addr1 - rd_addr2;
>            vout <= '1';
>         elsif rd_addr2 = 255 then
>            rd_addr2 <= 0;
>            state <= s2;
>         else
>            rd_addr2 <= rd_addr2 + 1;
>         end if;

noit doesn't work .see the picture attached

von dden (Guest)


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Hi,
why is the signal "distance" now aligned with the falling edge??
Maybe you don't know what you want, because by me the section works as 
you describe it.
Also what type of ram do you use, i think you don't use the ram right, 
for example your WE is ever 1?
And then you want to write an adresse and read 2 different adresses in 
one clock?
The next Question will be where your Calculations are going to ?

von basma (Guest)


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thanks alote pete it is working know . i need it for home work problems
thanks again

von basma (Guest)


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basma wrote:
> thanks alote pete it is working know . i need it for home work
> problems
> thanks again

basma wrote:
> thanks alote pete it is working know . i need it for home work
> problems
> thanks again
thanks dden alot

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