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Forum: FPGA, VHDL & Verilog state machine in vhdl


Author: Basma Hassan (Company: bhit) (basma)
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hi all,

i need to execute this state machine?
state machine of s0,s1,s2
s0: read ram1(address at 0) into ram1_data register, one clock,move to 
s1
s1:read ram2(address 0~till equality) into ram2 register, several 
clocks, if equality found between ram1/ram2 data set ram2 address
to zero, output (address difference), move to s2
s2:set ram1 address to 1(increment),one clock, move to s0
start again for ram1 address 1 and so on.
 i tried but it failed,
please ,any help ???
library ieee;
use ieee.std_logic_1164.all;

entity test is
    port(
        rst      : in  std_logic;
        clk      : in  std_logic;
        we       : in  std_logic;
        wr_data1 : in  std_logic_vector(7 downto 0);
        wr_data2 : in  std_logic_vector(7 downto 0);
        wr_addr  : in  integer range 0 to 255;
        distance : out integer range 0 to 255;
        vout     : out std_logic;
        no_match : out std_logic
         );
end entity;

architecture rtl of test is

signal rd_data1 : std_logic_vector(7 downto 0);
signal rd_data2 : std_logic_vector(7 downto 0);
signal rd_addr1 : integer range 0 to 255 := 0;
signal rd_addr2 : integer range 0 to 255 := 0;

type states is (s0,s1,s2);
signal state: states;

component wr_rd_ram
    port(
        clk      : in  std_logic;
        we       : in  std_logic;
        wr_data  : in  std_logic_vector(7 downto 0);
        wr_addr  : in  integer range 0 to 255;
        rd_addr  : in  integer range 0 to 255; 
        rd_data  : out std_logic_vector(7 downto 0)
         );
end component;

begin

ram1:wr_rd_ram
    port map(
        clk      => clk,
        we       => we,
        wr_data  => wr_data1,
        wr_addr  => wr_addr,
        rd_addr  => rd_addr1, 
        rd_data  => rd_data1
         );

ram2:wr_rd_ram
    port map(
        clk      => clk,
        we       => we,
        wr_data  => wr_data2,
        wr_addr  => wr_addr,
        rd_addr  => rd_addr2, 
        rd_data  => rd_data2
         );
----state machine 
process(rst,clk)
begin
if rst = '1' then
    state <= s0;
    vout <= '0';
    no_match <= '0';
    distance <= 0;
elsif rising_edge(clk) then

   vout <= '0';
   no_match <= '0';

   case state is
      when s0 =>
        rd_addr2 <= rd_addr2 + 1;
        if rd_data1 = rd_data2 then
           state <= s1;
           distance <= rd_addr1 - rd_addr2;
           vout <= '1';
        elsif rd_addr2 = 255 then
           rd_addr2 <= 0;
           state <= s2;
        end if;
 
      when s1 =>
        rd_addr1 <= rd_addr1 + 1;
        rd_addr2 <= 0;
        state <= s0;

      when s2 => 
         no_match <= '1';
         state <= s0;

      when others => null;

   end case;
end if;
end process;

end rtl;

: Edited by Moderator
Author: Innensechskant (Guest)
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Please try to be more specific about the issue.
What are the symptoms, the error messages or warnings which give you the 
impression that there is a failure?

Author: Basma Hassan (Company: bhit) (basma)
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the problem with state machine didn't gave me the correct result
----state machine
process(rst,clk)
begin
if rst = '1' then
    state <= s0;
    vout <= '0';
    no_match <= '0';
    distance <= 0;
elsif rising_edge(clk) then

   vout <= '0';
   no_match <= '0';

   case state is
      when s0 =>
        rd_addr2 <= rd_addr2 + 1;
        if rd_data1 = rd_data2 then
           state <= s1;
           distance <= rd_addr1 - rd_addr2;
           vout <= '1';
        elsif rd_addr2 = 255 then
           rd_addr2 <= 0;
           state <= s2;
        end if;

      when s1 =>
        rd_addr1 <= rd_addr1 + 1;
        rd_addr2 <= 0;
        state <= s0;

      when s2 =>
         no_match <= '1';
         state <= s0;

      when others => null;

   end case;
end if;
end process;

end rtl;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Basma Hassan wrote:
> the problem with state machine didn't gave me the correct result
How did you find that out? With a simulation? What do you expect? And 
what do you get? Are your RAMs working as expexted?
Pls. supply as much information as possible, its not funny to beg and 
plead for each piece of information... :-/

BTW: use the tokens [ vhdl ] and [ /vhdl ] (without the whitespaces) 
around your VHDL code. Then syntax highlighting makes reading much 
easier!

: Edited by Moderator
Author: Basma Hassan (Company: bhit) (basma)
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> How did you find that out? With a simulation? What do you expect? And
> what do you get? Are your RAMs working as expected?

i use xilinx 9.2i simulator ,we want to produce an array containing the 
distances from each element in memory1 to the element holding the same 
value in memory2. I.e searching for similarity, RAMs are worked well 
,the state machine is synthesize.i put my code previous assuming each 
element in the memory is std_logic_vector(0 to 7), and addresses from 0 
to 255.if the element in mem1 is 00010100 has address 2 & the same 
element in the mem2 has the address 10 the addresses difference(2-10)=8 
is the distance and so on.
i hope you understand me.thanks a lot.

: Edited by User
Author: dden (Guest)
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Lol, maybe you take a look at rd_addr2 and think again, its obvious when 
you simulate this, because rd_addr2 will never change and also maybe you 
also hang forever in s0.


Mfg

Author: Pete (Guest)
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Hmm why should rd_addr2 never change?

Author: Basma Hassan (Company: bhit) (basma)
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>its obvious when
> you simulate this, because rd_addr2 will never change and also maybe you
> also hang forever in s0
you mean the line rd_addr2=255;

Author: Pete (Guest)
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Hey Basama
Please tell us what failed. How did you tested? What was the outcome, 
output?

Author: Basma Hassan (Company: bhit) (basma)
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> Hey Basama
> Please tell us what failed. How did you tested? What was the outcome,
> output?

when i simulate the previous code the output distance always=0
i expected it to be such as 1+6+9+1+7+..... the distance between every 
element in mem1 and the same element in mem2.

Author: Pete (Guest)
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For me, your code seems to work. Maybe it's a problem with your 
simulation. Can you post the testbench?

Author: dden (Guest)
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you define for rd_addr1/2 an integer range 0 to 255 and then you 
calculate
 for example 0-1=?? if the data match, im sure your simulator gives a 
warning about this.

Author: basma (Guest)
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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?
i simulate without testbench
i smulate using testbench waveform

Author: dden (Guest)
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Hi,
and how did you test it using testbench waveform??
Should it look like the ones I attached?
There are also some incomplete Descriptions but it should "work", just 
make the changes I suggested.

For what do you design this?


Mfg

Author: basma (Guest)
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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?
hi,
the design is acts very well the problem if you see the picture attached 
is if rd_data1=rd_data2 then
rd_addr2 =0 but rd_data2 count the next element then start from 0 it 
make shift in rd_data2 and therefore count  false distance.
i want to do if data1=data2 then start from begining rd_data=0 and 
rd_data2=0 . i hope you understand me

Author: basma (Guest)
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then i want to sumation the all distance value .

Author: dden (Guest)
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Hi,
well then your problem is that you count every s0-State, even if 
rd1=rd2.
Try something like this:
      when s0 =>
        if rd_data1 = rd_data2 then
           state <= s1;
           distance <= rd_addr1 - rd_addr2;
           vout <= '1';
        elsif rd_addr2 = 255 then
           rd_addr2 <= 0;
           state <= s2;
        else
           rd_addr2 <= rd_addr2 + 1;
        end if;

Author: basma (Guest)
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Pete wrote:
> For me, your code seems to work. Maybe it's a problem with your
> simulation. Can you post the testbench?

dden wrote:
> Hi,
> well then your problem is that you count every s0-State, even if
> rd1=rd2.
> Try something like this:      when s0 =>
>         if rd_data1 = rd_data2 then
>            state <= s1;
>            distance <= rd_addr1 - rd_addr2;
>            vout <= '1';
>         elsif rd_addr2 = 255 then
>            rd_addr2 <= 0;
>            state <= s2;
>         else
>            rd_addr2 <= rd_addr2 + 1;
>         end if;

noit doesn't work .see the picture attached

Author: dden (Guest)
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  • preview image for 1.jpg
    1.jpg
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  • preview image for 2.jpg
    2.jpg
    136 KB, 88 downloads

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Hi,
why is the signal "distance" now aligned with the falling edge??
Maybe you don't know what you want, because by me the section works as 
you describe it.
Also what type of ram do you use, i think you don't use the ram right, 
for example your WE is ever 1?
And then you want to write an adresse and read 2 different adresses in 
one clock?
The next Question will be where your Calculations are going to ?

Author: basma (Guest)
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thanks alote pete it is working know . i need it for home work problems
thanks again

Author: basma (Guest)
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basma wrote:
> thanks alote pete it is working know . i need it for home work
> problems
> thanks again

basma wrote:
> thanks alote pete it is working know . i need it for home work
> problems
> thanks again
thanks dden alot

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