i need to execute this state machine?
state machine of s0,s1,s2
s0: read ram1(address at 0) into ram1_data register, one clock,move to
s1:read ram2(address 0~till equality) into ram2 register, several
clocks, if equality found between ram1/ram2 data set ram2 address
to zero, output (address difference), move to s2
s2:set ram1 address to 1(increment),one clock, move to s0
start again for ram1 address 1 and so on.
i tried but it failed,
please ,any help ???
Basma Hassan wrote:> the problem with state machine didn't gave me the correct result
How did you find that out? With a simulation? What do you expect? And
what do you get? Are your RAMs working as expexted?
Pls. supply as much information as possible, its not funny to beg and
plead for each piece of information... :-/
BTW: use the tokens [ vhdl ] and [ /vhdl ] (without the whitespaces)
around your VHDL code. Then syntax highlighting makes reading much
> How did you find that out? With a simulation? What do you expect? And> what do you get? Are your RAMs working as expected?
i use xilinx 9.2i simulator ,we want to produce an array containing the
distances from each element in memory1 to the element holding the same
value in memory2. I.e searching for similarity, RAMs are worked well
,the state machine is synthesize.i put my code previous assuming each
element in the memory is std_logic_vector(0 to 7), and addresses from 0
to 255.if the element in mem1 is 00010100 has address 2 & the same
element in the mem2 has the address 10 the addresses difference(2-10)=8
is the distance and so on.
i hope you understand me.thanks a lot.
> Hey Basama> Please tell us what failed. How did you tested? What was the outcome,> output?
when i simulate the previous code the output distance always=0
i expected it to be such as 1+6+9+1+7+..... the distance between every
element in mem1 and the same element in mem2.
and how did you test it using testbench waveform??
Should it look like the ones I attached?
There are also some incomplete Descriptions but it should "work", just
make the changes I suggested.
For what do you design this?
Pete wrote:> For me, your code seems to work. Maybe it's a problem with your> simulation. Can you post the testbench?
the design is acts very well the problem if you see the picture attached
is if rd_data1=rd_data2 then
rd_addr2 =0 but rd_data2 count the next element then start from 0 it
make shift in rd_data2 and therefore count false distance.
i want to do if data1=data2 then start from begining rd_data=0 and
rd_data2=0 . i hope you understand me
Pete wrote:> For me, your code seems to work. Maybe it's a problem with your> simulation. Can you post the testbench?dden wrote:> Hi,> well then your problem is that you count every s0-State, even if> rd1=rd2.> Try something like this: when s0 =>> if rd_data1 = rd_data2 then> state <= s1;> distance <= rd_addr1 - rd_addr2;> vout <= '1';> elsif rd_addr2 = 255 then> rd_addr2 <= 0;> state <= s2;> else> rd_addr2 <= rd_addr2 + 1;> end if;
noit doesn't work .see the picture attached
why is the signal "distance" now aligned with the falling edge??
Maybe you don't know what you want, because by me the section works as
you describe it.
Also what type of ram do you use, i think you don't use the ram right,
for example your WE is ever 1?
And then you want to write an adresse and read 2 different adresses in
The next Question will be where your Calculations are going to ?
basma wrote:> thanks alote pete it is working know . i need it for home work> problems> thanks againbasma wrote:> thanks alote pete it is working know . i need it for home work> problems> thanks again
thanks dden alot