EmbDev.net

Forum: FPGA, VHDL & Verilog State Machines for an equation


State Machines for an equation
Author: Hassan M. (Company: Namal) (hasu)
Posted on:
Attached files:
Rate this post
0 ▲ useful
▼ not useful 
Dear All,

I have attached a file which is comprised of matlab code for the 
coriolis force acting on water parcel in a lake, I want to convert it to 
verilog but I have confusion that how should I start my work? I have 
studied state machines but unable to relate the concept of ASM with my 
problem. Please help to remove my confusion.

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.