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Clear_preset flip flop inputs BK_Coder 2
UART doesn't stop transmitting and sends wrong value helloGuys 2
OS on a fpga Mark L. 12
How to generate Trigger for 500ns in Verilog ? Saraswathy S. 0
initializing oled display using vhdl Alex H. 2
code transfer from iar to gcc compiler Cetin Cetn 2
Designated Number Counter and Cycle counter 2 Digit Jason Wang 13
FT4222H Problem avi 1
Interfacing ADC with FPGA Varun Chitransh 3
What microcontroller is this? [image] Tim 8
Simulink Voltage-to-Frequency Converter on matlab. Bùi Cường 3
oscillator 50MHz Dima Potapov 5
AIL EATON 2075B-205 DH6SBN 1
New to VHDL Need help with this assignment James Yang 8
APA102 led strip with altera DE2-115 Board Peter 3
Quartus II TCL script to try multiple fitter seed settings? andi6510 4
flop-flop simulation in ModelSim Dima Potapov 19
is at left hand side of signal assignment statement. Wilson Torres 2
Simple Test of Chans Lib STM32 SD CARD SPI + FAT (Chan) 0
Control brightness of LEDs using VHDL Tanjila Tahsin 1
16-bit ALU from 1- bit ALU Mitsos Mitsos 3
Syntax Error Rectification Rejoy Mathews 0
Microprocessor Datapath FSM Controller Ed Hower 0
Xilinx Custom IP accessing 16-bit bram gundamz2001 2
Learning FPGA DE10 Nano Nirav Shah 3
ADC on DEO NANO not working chinmaye 3
HELP VHDL code for ADC at FPGA Locked vicky d. 13
How about a low pass filter followed by LTC6085 and then to the ADC KW40Z sound? Elijah Clark 2
Self-Inductance calculation Nico N. 0
Verilog Data Type Rejoy Mathews 2
reading from micro-controller Sarah John 2
what is this ? Ritesh Kakkar 6
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for TienNguyen 5
Verilog task yield "x" for a variable in a timestep Frank Li 4
FPGA image fusion & stereo vision Karamazov 4
bits_counter meido 4
Width Mismatch in RAM Design Ed Hower 5
Verilog code for modulus of negative number query Lakshita J. 3
PSEUDORANDOM NUMBER GENERATOR AND HAMMING CODE DISPLAY ON LED Test Bench Ed Hower 5
Verilog Query Jay 5
cheap fpga for starting Sylvana Windrunner 13
VHDL UART how to handle incoming bytes? Macellan Macellan 0
Implement function for three architectures using VHDL Sergey Levko 1
Controlling the tasks Sushma K S 0
10k Poti for a DAC and Arduino? Fadi Safadi 1
Suggestion on controller selection Aravind MR 5
IP with axi-stream slave and axi4-full master interface zyed 1
Looking for a comparator IC with programmable threshold cmppt 0
Frequency follower Ste_Trat 13
VIVADO IP integration Elico C. 0
IP with axi-stream slave and axi4-full master interface zyed 0