Forum: FPGA, VHDL & Verilog Task in verilog for sending the responses for respective address

von Sushma K. (Company: None) (digital_treasure)

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I trying to write a task to be called in my test bench which will send a 
sequence of data back to DUT as per the address received from DUT. In 
RTL, the address is sent always starting from 0 and then it is 
incremented periodically from 0-15 (they have used a counter). What I 
need to do is when I receive a address 0 , I should send the data for 
address-0 and then keep on sending the data of addresses from 1 to till 
15, on receiving the address. I am not sure about the below code. Any 
help is appreciated.

 task give_answer;

input[3:0] address;

    4'b0000: begin  data =8'b10100101; end
    4'b0001: begin  data =8'b00011101; end
    4'b0010: begin  data =8'b11010111; end
    4'b0011: begin  data =8'b11100110; end
    4'b0100: begin  data =8'b11111110; end
    4'b0101: begin  data =8'b11110011; end
    4'b0110: begin  data =8'b00111110; end
    4'b0111: begin  data =8'b11000100; end
    4'b1000: begin  data =8'b10101101; end
    4'b1001: begin  data =8'b10001111; end
    4'b1010: begin  data =8'b00101111; end
    4'b1011: begin  data =8'b00001001; end
    4'b1100: begin  data =8'b11000110; end
    4'b1101: begin  data =8'b11001010; end
    4'b1110: begin  data =8'b01000110; end
    4'b1111: begin  data =8'b00010000; end
    default: begin  data =8'b10100101; end


von Lothar M. (lkmiller) (Moderator)

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Sushma K. wrote:
> I am not sure about the below code.
Whats the problem with it?
How does the simulation results look like?

> Any help is appreciated.
You must ask a specific question to get a specific answer.

von Andy (Guest)

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You need to declare also the data output:

output [7:0] data;

And the @(address) looks strange.
You also don't need so many begin / end. This makes it a bit unreadable.


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