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Forum: FPGA, VHDL & Verilog Syntax Error Rectification


Author: Rejoy Mathews (Company: Lab Instructor) (rejoymathews32)
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module State_Machine(
    input button_start,
    input marbles,
    input clk,
    input player_turn_complete,
    output reg turn
    );

    reg [2:0] state;

    initial begin
        state = 0;
        turn = 0;
    end

    always @(posedge clk) begin
        case(state)
            3'b000:
                if(button_start == 1) state = 1; //button press to start 
playing
                else state = 0;
            3'b001:
                turn = 1;
                if(player_turn_complete == 1) state = 2;
                else state = 1;
        endcase
    end
endmodule

I get a syntax error near if at 'if(player_turn_complete == 1) state = 
2;'. Can someone kindly rectify the same. I am unable to figure out the 
syntax error here.

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