Forum: FPGA, VHDL & Verilog facing intra clock path setup violations

von jose (Guest)

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hello ecveryone,

i am working on a project where i am sending data from fpga (zynq) to
linux pc at 125 MHZ  and everything worked fine. when i moved to higher
frequency 250 MHZ (because next step of development is to add a hardware
that works at higher frequency) i am facing intra clock path setup
violations. and this happens inside a interconnect that has 1 slave
(input with  freq f1)and 2 master(output with  freq f1 and f2). the 2
master function at different frequency . the violations occur in one of
the master output between the signals inside couplers module and the
frequencyis same

things i tried...
1)added axi register slice at each interface of interconnect.
2)changed optimisation statergy  option of interconnect.
3)opt design in implementation settings.

none of the above worked.
looking for your valuable suggestions.


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