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Forum: FPGA, VHDL & Verilog Cpu: why only on posedge?


Author: Mark L. (markl)
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Hi,
I've been training my fpga skills but I still have a question.

https://github.com/ejrh/cpu/blob/master/rtl/alu.v

This page is a cpu ALU.
I am wondering why we should wait on a posedge to restrict the execution 
flow. We could have better parallelism, albeit with a supporting 
compiler.

Thanks

Author: C. A. Rotwang (Guest)
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Mark L. wrote:

> I am wondering why we should wait on a posedge to restrict the execution
> flow. We could have better parallelism, albeit with a supporting
> compiler.

There are asynchrounous designs but mostly there a larger than the 
synchronous ones.

http://haltenraum.com/article/asynchrone-schaltung
https://en.wikipedia.org/wiki/Asynchronous_circuit
http://www.tkt.cs.tut.fi/kurssit/3520/K13/CH_16.pdf
https://en.wikipedia.org/wiki/C-element

Author: Mark L. (markl)
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Ok, so  if I understand correctly adding negedge is a bad idea here

Author: Lothar M. (lkmiller) (Moderator)
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Mark L. wrote:
> wondering why we should wait on a posedge to restrict the execution flow.
How do you expect to get a working adresscounter without a clock? (a 
hint: a "combinatorial loop" is usually not desirable in a design).
How would you read code without an consistent adresscounter?

Mark L. wrote:
> Ok, so  if I understand correctly adding negedge is a bad idea here
It virtually doubles the clock frequency in your design. Because it 
leaves you only half the time to setup for the next active clock edge.
In fact due to an asymmetric clock it's a little bit more than factor 2.

: Edited by Moderator
Author: Mark L. (markl)
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I get it,
So with a negedge, the whole system becomes unpredictable, but may work 
if everything is perfectly timed. And that would be insane to rely on 
such a system (correct?)

The more I progress, the more I realize the kind of hobby I am into.

Thanks

: Edited by User
Author: Lothar M. (lkmiller) (Moderator)
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Mark L. wrote:
> So with a negedge, the whole system becomes unpredictable
No, it's perfectly predictable as long as you specify the clock 
correctly to the toolchain.

When having only one active clock edge (only rising or falling) and your 
logic needs 10ns to get stable then you get something around 100MHz.

When using both edges as active edges and your logic needs 10ns to get 
stable, then you need that time between two consecutive edges, then you 
must halve your clock frequency to 50MHz.

So at the end nothing is won.

Author: Mark L. (markl)
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I get it now.

Thank you so much Lothar, your help is invaluable.

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