flop-flop simulation in ModelSim

Dima P. wrote:
> What is it?
Depends somewhat on your code...

But by default blue means high-Z.

testbench tdff.v

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module top; 

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   reg clk; 

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   reg [1:0] in_inf; 

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   wire [1:0] out_inf;

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dff D1 (clk, in_inf, out_inf); 

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initial // Clock generator

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  begin

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    clk = 0;

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    forever #10 clk = !clk;

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  end

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initial //in_inf[0]  

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  begin

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    in_inf[0] = 0;

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    #28 in_inf[0] = 1;

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    #5 in_inf[0] = 0;

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  end

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initial  //in_inf[1]  

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  begin

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    in_inf[1] = 0;

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    #48 in_inf[1] = 1;

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    #5 in_inf[1] = 0;

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  end

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endmodule

whats the difference between in_inf[0] and in_inf[1]

Dima P. wrote:
> whats the difference between in_inf[0] and in_inf[1]
Thats remains the question.
What you posted is the test bench. That obvoiusly works properly...

thanks, but why out_inf[1] is hi-z? how do i see normal(not blue) signal 
as out_inf[1]?

Dima P. wrote:
> thanks, but why out_inf[1] is hi-z?
Thats in the up to now secret code of the flipflop itself. What you 
posted generates the clk and the in_inf signals. And they are fine.

thanks, the bug in the "secret code" indeed ))

And whats mean red signal 1'hx out_inf[0]?

But the signal must be zero (not unknown)

Dima P. wrote:
> But the signal must be zero (not unknown)
'U' does NOT mean "Unknown"! 'U' is "Uninitialized".

Why don't you show your code for better guessing?

new dff.v

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module dff(clk, din, dout); 

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  input clk; 

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  input [1:0] din; 

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  output [1:0] dout; 

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reg [1:0] dout; 

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 always @ (posedge clk) 

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  begin 

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   dout <= din; 

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end 

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endmodule

new tdff.v

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module top; 

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   reg clk; 

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   reg [1:0] in_inf; 

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   wire [1:0] out_inf;

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dff D1 (clk, in_inf, out_inf); 

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initial 

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  begin

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  in_inf[0] = 0;

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  in_inf[1] = 0;

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  clk = 0;

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#28 in_inf[0] = 1;

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#5 clk = 1;

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#10 in_inf[0] = 0;

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#5 clk = 0;

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end

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endmodule

That looks OK, what's the problem with it?

the signal is red (before first clock). Why?

can i initialize value before first clock?

i try to initialize value in dff.v

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module dff(clk, dout); 

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  input clk; 

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  output reg [1:0] dout; 

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reg [1:0] din;

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initial

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  begin

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    din[0] = 1'b0;

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    din[1] = 1'b0;

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  end 

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always @ (posedge clk) 

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  begin 

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   dout <= din; 

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  end 

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endmodule

testbench doesnt work

Dima P. wrote:
> testbench doesnt work
What message?

> i try to initialize value in dff.v
As you can easily see: dout is making trouble to you. And therefore you 
must initialize dout. That are your flipflops!

ok, thank you