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Forum: FPGA, VHDL & Verilog flop-flop simulation in ModelSim


von Dima P. (demsp)


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i try to simulate [1:0]flip-flop in ModelSim and i see one normal 
signal(out_inf[0]) and one blue signal(out_inf[1]). What is it?

von Lothar M. (lkmiller) (Moderator)


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Dima P. wrote:
> What is it?
Depends somewhat on your code...

But by default blue means high-Z.

von Dima P. (demsp)


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testbench tdff.v
1
module top; 
2
   reg clk; 
3
   reg [1:0] in_inf; 
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   wire [1:0] out_inf;
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dff D1 (clk, in_inf, out_inf); 
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initial // Clock generator
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  begin
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    clk = 0;
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    forever #10 clk = !clk;
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  end
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initial //in_inf[0]  
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  begin
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    in_inf[0] = 0;
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    #28 in_inf[0] = 1;
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    #5 in_inf[0] = 0;
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  end
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initial  //in_inf[1]  
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  begin
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    in_inf[1] = 0;
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    #48 in_inf[1] = 1;
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    #5 in_inf[1] = 0;
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  end
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endmodule

whats the difference between in_inf[0] and in_inf[1]

von Lothar M. (lkmiller) (Moderator)


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Dima P. wrote:
> whats the difference between in_inf[0] and in_inf[1]
Thats remains the question.
What you posted is the test bench. That obvoiusly works properly...

von Dima P. (demsp)


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thanks, but why out_inf[1] is hi-z? how do i see normal(not blue) signal 
as out_inf[1]?

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Dima P. wrote:
> thanks, but why out_inf[1] is hi-z?
Thats in the up to now secret code of the flipflop itself. What you 
posted generates the clk and the in_inf signals. And they are fine.

von Dima P. (demsp)


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thanks, the bug in the "secret code" indeed ))

von Dima P. (demsp)


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And whats mean red signal 1'hx out_inf[0]?

von Dussel (Guest)


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Dima P. wrote:
> And whats mean red signal 1'hx out_inf[0]?
Behind the h is the value of the signal, in this case X. If you look up 
the definition of std_(u)logic you see, that this means 'unknown'. (Like 
Z means 'High Impedance')

von Dima P. (demsp)


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But the signal must be zero (not unknown)

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von Dussel (Guest)


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Probably the signal is not initialised. The signal is assigned a value 
on the rising edge of the clock. So before the first rising edge, there 
is no assignment, so the signal value is unknown.
But I'd expect U instead of X.

von Lothar M. (lkmiller) (Moderator)


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Dima P. wrote:
> But the signal must be zero (not unknown)
'U' does NOT mean "Unknown"! 'U' is "Uninitialized".

Why don't you show your code for better guessing?

von Dima P. (demsp)


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new dff.v
1
module dff(clk, din, dout); 
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  input clk; 
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  input [1:0] din; 
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  output [1:0] dout; 
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reg [1:0] dout; 
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 always @ (posedge clk) 
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  begin 
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   dout <= din; 
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end 
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endmodule

new tdff.v
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module top; 
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   reg clk; 
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   reg [1:0] in_inf; 
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   wire [1:0] out_inf;
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dff D1 (clk, in_inf, out_inf); 
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initial 
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  begin
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  in_inf[0] = 0;
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  in_inf[1] = 0;
10
  clk = 0;
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#28 in_inf[0] = 1;
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#5 clk = 1;
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#10 in_inf[0] = 0;
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#5 clk = 0;
15
end
16
endmodule

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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That looks OK, what's the problem with it?

von Dima P. (demsp)


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the signal is red (before first clock). Why?

: Edited by User
von Dussel (Guest)


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Dima P. wrote:
> the signal is red (before first clock). Why?
I explained before.
Which value do you expect and why?

von Dima P. (demsp)


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can i initialize value before first clock?

: Edited by User
von Dima P. (demsp)


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i try to initialize value in dff.v
1
module dff(clk, dout); 
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  input clk; 
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  output reg [1:0] dout; 
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reg [1:0] din;
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initial
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  begin
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    din[0] = 1'b0;
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    din[1] = 1'b0;
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  end 
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always @ (posedge clk) 
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  begin 
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   dout <= din; 
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  end 
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endmodule

testbench doesnt work

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Dima P. wrote:
> testbench doesnt work
What message?

> i try to initialize value in dff.v
As you can easily see: dout is making trouble to you. And therefore you 
must initialize dout. That are your flipflops!

: Edited by Moderator
von Dima P. (demsp)


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ok, thank you

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