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Forum: FPGA, VHDL & Verilog flop-flop simulation in ModelSim


Author: Dima P. (demsp)
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i try to simulate [1:0]flip-flop in ModelSim and i see one normal 
signal(out_inf[0]) and one blue signal(out_inf[1]). What is it?

Author: Lothar M. (lkmiller) (Moderator)
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Dima P. wrote:
> What is it?
Depends somewhat on your code...

But by default blue means high-Z.

Author: Dima P. (demsp)
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testbench tdff.v
module top; 
   reg clk; 
   reg [1:0] in_inf; 
   wire [1:0] out_inf;
dff D1 (clk, in_inf, out_inf); 

initial // Clock generator
  begin
    clk = 0;
    forever #10 clk = !clk;
  end

initial //in_inf[0]  
  begin
    in_inf[0] = 0;
    #28 in_inf[0] = 1;
    #5 in_inf[0] = 0;
  end
initial  //in_inf[1]  
  begin
    in_inf[1] = 0;
    #48 in_inf[1] = 1;
    #5 in_inf[1] = 0;
  end
endmodule 

whats the difference between in_inf[0] and in_inf[1]

Author: Lothar M. (lkmiller) (Moderator)
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Dima P. wrote:
> whats the difference between in_inf[0] and in_inf[1]
Thats remains the question.
What you posted is the test bench. That obvoiusly works properly...

Author: Dima P. (demsp)
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thanks, but why out_inf[1] is hi-z? how do i see normal(not blue) signal 
as out_inf[1]?

: Edited by User
Author: Lothar M. (lkmiller) (Moderator)
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Dima P. wrote:
> thanks, but why out_inf[1] is hi-z?
Thats in the up to now secret code of the flipflop itself. What you 
posted generates the clk and the in_inf signals. And they are fine.

Author: Dima P. (demsp)
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thanks, the bug in the "secret code" indeed ))

Author: Dima P. (demsp)
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And whats mean red signal 1'hx out_inf[0]?

Author: Dussel (Guest)
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Dima P. wrote:
> And whats mean red signal 1'hx out_inf[0]?
Behind the h is the value of the signal, in this case X. If you look up 
the definition of std_(u)logic you see, that this means 'unknown'. (Like 
Z means 'High Impedance')

Author: Dima P. (demsp)
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But the signal must be zero (not unknown)

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Author: Dussel (Guest)
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Probably the signal is not initialised. The signal is assigned a value 
on the rising edge of the clock. So before the first rising edge, there 
is no assignment, so the signal value is unknown.
But I'd expect U instead of X.

Author: Lothar M. (lkmiller) (Moderator)
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Dima P. wrote:
> But the signal must be zero (not unknown)
'U' does NOT mean "Unknown"! 'U' is "Uninitialized".

Why don't you show your code for better guessing?

Author: Dima P. (demsp)
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new dff.v
module dff(clk, din, dout); 
  input clk; 
  input [1:0] din; 
  output [1:0] dout; 
reg [1:0] dout; 
 always @ (posedge clk) 
  begin 
   dout <= din; 
end 
endmodule 

new tdff.v
module top; 
   reg clk; 
   reg [1:0] in_inf; 
   wire [1:0] out_inf;
dff D1 (clk, in_inf, out_inf); 
initial 
  begin
  in_inf[0] = 0;
  in_inf[1] = 0;
  clk = 0;
#28 in_inf[0] = 1;
#5 clk = 1;
#10 in_inf[0] = 0;
#5 clk = 0;
end
endmodule 

: Edited by User
Author: Lothar M. (lkmiller) (Moderator)
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That looks OK, what's the problem with it?

Author: Dima P. (demsp)
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the signal is red (before first clock). Why?

: Edited by User
Author: Dussel (Guest)
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Dima P. wrote:
> the signal is red (before first clock). Why?
I explained before.
Which value do you expect and why?

Author: Dima P. (demsp)
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can i initialize value before first clock?

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Author: Dima P. (demsp)
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i try to initialize value in dff.v
module dff(clk, dout); 
  input clk; 
  output reg [1:0] dout; 

reg [1:0] din;
initial
  begin
    din[0] = 1'b0;
    din[1] = 1'b0;
  end 

always @ (posedge clk) 
  begin 
   dout <= din; 
  end 
endmodule 

testbench doesnt work

: Edited by User
Author: Lothar M. (lkmiller) (Moderator)
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Dima P. wrote:
> testbench doesnt work
What message?

> i try to initialize value in dff.v
As you can easily see: dout is making trouble to you. And therefore you 
must initialize dout. That are your flipflops!

: Edited by Moderator
Author: Dima P. (demsp)
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ok, thank you

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