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Forum: FPGA, VHDL & Verilog Clear_preset flip flop inputs


Author: BK_Coder (Guest)
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Hi All

If I am writing a VHDL code, for a flip flop that includes clear and 
reset inputs, both active when 'low', how do i make provision for this 
for the case when clear = 0 and preset=0, that is the case that produces 
invalid output (ie to be excluded/avoided). Do i just exclude defining 
this logic in the code? or should i code logic statements that instruct 
VHDL to avoid this situation of these inputs being both active same 
time? e.g. IF (clr = '0' and pres='0') then. .......

Regards
Bk

Author: Vancouver (Guest)
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Make your FF module 'waterproof'. Catch this condition inside the module 
and decide what to do, e.g. ignoring (no state change), giving priority 
to clear, whatever. If this condition may drive your design in an 
undefined state, you have to handle it.

Author: Lothar M. (lkmiller) (Moderator)
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BK_Coder wrote:
> If I am writing a VHDL code, for a flip flop that includes clear and
> reset inputs
Are those inputs synchronous or asynchronous inputs?

If the second, then there will be big trouble toget the design running 
properly...

> for a flip flop that includes clear and reset inputs
Indeed you only have exactly those flipflops already installed on the 
FPGA. So have a close look to the data sheet of your specific FPGA.

Have a look there and try something similar with your toolchain:
Beitrag "Re: Hardware mit VHDL "richtig" beschreiben."
Try Google translate, its German... ;-)

: Edited by Moderator

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