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Forum: FPGA, VHDL & Verilog LRM. 10.4.2 non blocking synthesis


Author: Mark L. (markl)
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Hi,

I read the LRM 1800-2017, section 4 and section 10.4.x

The standard keeps talking about what the simulator does in case of non 
blocking assignment in regard with the event regions.

But how does this translate at the hardware level? the simulation does a 
lot of things but the more I read, the more I wonder if there is a risk 
of a mismatch between simulation and synthesis.

For example, if I have five parallel always block fighting to update a 
common value (synthesizable mutex) how will that be implemented in 
hardware? Will the standard be respected and will each non blocking 
update be executed in the absolute order they appeared?

I am now full of doubts, please help

: Edited by User
Author: Mark L. (markl)
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anything wrong with my question?

Author: Duke Scarring (Guest)
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Mark L. wrote:
> But how does this translate at the hardware level?
You have one design description (your code).
This is used by the simulator (compile+execute) for simulation.
The same code is also used by the synthesizer (uually the tool from your 
FPGA vendor) to activate the right connections in your FPGA.

The code is the same, but both tools (simulator and syntesizer) are 
unrelated.

Duke

Author: Mark L. (markl)
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Thanks,

My doubts are now relieved.

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