16-bit ALU from 1- bit ALU

Start time: 09:27:37 on May 08,2018

vcom ALU1.vhd

Model Technology ModelSim SE-64 vcom 10.6c Compiler 2017.07 Jul 26 2017

-- Loading package STANDARD

-- Loading package TEXTIO

-- Loading package std_logic_1164

-- Compiling entity fulladd

-- Compiling architecture logic of fulladd

-- Compiling entity substraction

-- Compiling architecture sub of substraction

-- Compiling entity ALU1

-- Compiling architecture Structural of ALU1

-- Compiling entity Ripple_Adder

-- Compiling architecture Structural of Ripple_Adder

###### ALU1.vhd(109): A1: ALU1 port map( A(0), B(0), Cin, S(0), c1);

** Error: ALU1.vhd(109): Cannot resolve indexed name (type ieee.std_logic_1164.STD_ULOGIC) as type ieee.std_logic_1164.STD_LOGIC_VECTOR.

** Error: ALU1.vhd(109): Signal "c1" is type ieee.std_logic_1164.STD_LOGIC; expecting type std.STANDARD.BIT.

** Error: ALU1.vhd(109): (vcom-1035) Formal port "Aiv" has OPEN or no actual associated with it.

...

...

...

** Error: ALU1.vhd(126): VHDL Compiler exiting

End time: 09:27:37 on May 08,2018, Elapsed time: 0:00:00

Errors: 49, Warnings: 0

A1: ALU1 port map( A(0), B(0), Cin, S(0), c1);

component ALU1 is

    Port ( Oper:in STD_LOGIC_VECTOR(2 DOWNTO 0);

       a, b, Cin: in STD_LOGIC;

       Biv ,Aiv: in BIT;

        R, Cout: out STD_LOGIC);

end component;