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Forum: FPGA, VHDL & Verilog oscillator 50MHz


Author: Dima P. (demsp)
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Author: Lothar M. (lkmiller) (Moderator)
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It looks to me that no information on that webpage (schmatics, pictures, 
layout) matches the other. So just order one and look what you get and 
where the pin 64 (Global Clock 3) of the CPLD goes to...

Author: Dima P. (demsp)
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Global Clock 3 - what is it?

: Edited by User
Author: Schlumpf (Guest)
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Wrong schematic!!

On this site you find the link to board´s schematic:

https://www.openimpulse.com/blog/products-page/product-category/max-ii-epm240-cpld-minimal-development-board/

Author: Lothar M. (lkmiller) (Moderator)
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Whats the actual problem?
Do you not know how to connect your HDL design to the clock pin 64?
Or do you not know how to connect a clock to the pin 64?

Dima P. wrote:
> Global Clock 3 - what is it?
Read the manual of the CPLD according to the pin 64 named GCLK3...

: Edited by Moderator
Author: Dima P. (demsp)
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Now I get it, thanks.

: Edited by User

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