EmbDev.net

Forum: FPGA, VHDL & Verilog oscillator 50MHz


von Dima P. (demsp)


Rate this post
useful
not useful

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
It looks to me that no information on that webpage (schmatics, pictures, 
layout) matches the other. So just order one and look what you get and 
where the pin 64 (Global Clock 3) of the CPLD goes to...

von Dima P. (demsp)


Rate this post
useful
not useful
Global Clock 3 - what is it?

: Edited by User
von Schlumpf (Guest)


Rate this post
useful
not useful
Wrong schematic!!

On this site you find the link to board´s schematic:

https://www.openimpulse.com/blog/products-page/product-category/max-ii-epm240-cpld-minimal-development-board/

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Attached files:

Rate this post
useful
not useful
Whats the actual problem?
Do you not know how to connect your HDL design to the clock pin 64?
Or do you not know how to connect a clock to the pin 64?

Dima P. wrote:
> Global Clock 3 - what is it?
Read the manual of the CPLD according to the pin 64 named GCLK3...

: Edited by Moderator
von Dima P. (demsp)


Rate this post
useful
not useful
Now I get it, thanks.

: Edited by User
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.