James Y. wrote:
> Here's some partial clue codes provided by professor,of course with some
> errors need to correct...
What are your suggestions? What error messages does the toolchain 
report?  What's wrong in the erronous lines?


James Y. wrote:
> Thanks guys for any thoughts and guide me through this.
It's your homework, when you give some reasonable suggestions then maybe 
someone will help you further on.

Lothar M. wrote:
> James Y. wrote:
>> Here's some partial clue codes provided by professor,of course with some
>> errors need to correct...
> What are your suggestions? What error messages does the toolchain
> report?  What's wrong in the erronous lines?
> signal ck1hz : STD_LOGIC_VECTOR (24); <-The expression can not be converted to 
type STD_LOGIC_VECTOR.
Q <= Q + '1'; <- + can not have such operands in this context.
ck1hz <= Q(24) => Y when DIR = '1' else DIR = '0'; <- Undefined symbol 
'ck1hz'. & parse error, unexpected ROW, expecting SEMICOLON
>
> James Y. wrote:
>> Thanks guys for any thoughts and guide me through this.
> It's your homework, when you give some reasonable suggestions then maybe
> someone will help you further on.
I know I supposed to work out my own homework,but I'm honestly out of 
ideas,and the clues aren't helping...I can't see the points where I need 
to do.

James Y. wrote:
> I can't see the points where I need to do.
You have a sketch of a hardware you have to describe with VHDL.
So
1. describe the prescaler for the 1.5 Hz and
2. the 4 bit counter, connect
3. them together and
4. to the 7 segment decoder.

James Y. wrote:
> signal ck1hz : STD_LOGIC_VECTOR (24);
Looks like this should be an alias of Q(24)

> process (CLK,Q)
There are too much sichals in the sensitivity list here.
clk is enough.

> Undefined symbol 'ck1hz'.
Define it in a proper way. And define its name in a way that it matches 
the real world: you do not want a 1 Hz clock, you want 1.5 Hz.
BTW: are 1.562 Hz close enough to the 1.5 Hz you want? Then maybe you 
can head on with your "2^24 prescaler clock divider", although you 
should not use such a "clock-divider-prescaler" design strategy in 
modern FPGAs.

Do you have to use as much as you can from that very old fashioned 
example? Or can you write code thats more up to date? Code with clock 
enables and so on?


All in all my attempt would look like this:

1

...

2

use IEEE.NUMERIC_STD.ALL;

3

...

4

signal prescaler : integer range 0 to 33333332 := 0; -- 1.5Hz = 50000000/1.5

5

signal index     : integer range 0 to 15 := 0;

6

signal clockenable1hz5: STD_LOGIC;

7

8

begin

9

10

-- prescaler

11

process begin

12

   wait until rising_edge(clk);  -- only 1 clock throughout the whole design!

13

   if prescaler < 33333332 then 

14

      clockenable1hz5 <= '0';    

15

      prescaler       <= prescaler+1;

16

   else

17

      clockenable1hz5 <= '1';     -- generate a clock enable with 1.5 Hz

18

      prescaler       <= 0;

19

   end if;

20

end process;

21

22

-- index counter

23

process begin

24

   wait until rising_edge(clk);  -- only 1 clock throughout the whole design!

25

   if clockenable1hz5 = '1' then

26

      if index < 15 then  index <= index+1;

27

      else                index <= 0;

28

      end if;

29

   end if;

30

end process;

31

32

-- the decoder

33

with index select 

34

   C <= "1000000" when 0, 

35

        "1111001" when 1,

36

        "0100100" when 2, 

37

        "0110000" when 3, 

38

        "0011001" when 4, 

39

        "0010010" when 5, 

40

        ....

41

        "0000110" when 14,

42

        "0001110" when 15;

All in all that coding style is far more read- and understandable for 
humans. And thats the style I'm teaching my students...

Lothar M. wrote:
> Do you have to use as much as you can from that very old fashioned
> example? Or can you write code thats more up to date? Code with clock
> enables and so on?
I can't be sure,but I don't think there is any limitation.

C. A. Rotwang wrote:
> Check with the internet how to code an incrementing counter in VHDL.
> It's important to use the approbiate types und libraries and not to be
> confused with the differences beetwenn 1 and '1'.
Ok,I'll try to google more information about it as possible.

Lothar M. wrote:
> All in all that coding style is far more read- and understandable for
> humans. And thats the style I'm teaching my students...
And may I ask,can you recommend a book for me to study VHDL?(I'm using 
Xilinx ISE)