I am working with FPGA board. For my test, i am going to add the trigger
logic in one side [One PC], and in other side the counter design will be
added in XILIXN VIVADO and should start to give its counter after
receiving the trigger signal.
For every trigger [500ns], the counter should start. To execute this
task, i need the verilog code for Creating the Trigger Signal.
1 | module counter(
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2 | input clk,
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3 | input reset,
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4 | output [127:0] counter_out,
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5 | output trig
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6 | );
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7 |
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8 | reg trig=0;
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9 | reg [127:0] counter_out=0;
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10 | reg [7:0] temp=0;
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11 |
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12 | always@(posedge clk)
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13 | begin
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14 | if(~reset)
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15 | begin
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16 | trig<=0;
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17 | counter_out<=0;
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18 | end
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19 | else
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20 | begin
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21 | counter_out<=counter_out+1;
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22 | temp<=temp+1;
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23 | if(temp==25)
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24 | begin
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25 | temp<=0;
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26 | trig<=~trig;
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27 | end
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28 | end
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29 | end
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30 | endmodule
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