I am working with FPGA board. For my test, i am going to add the trigger logic in one side [One PC], and in other side the counter design will be added in XILIXN VIVADO and should start to give its counter after receiving the trigger signal. For every trigger [500ns], the counter should start. To execute this task, i need the verilog code for Creating the Trigger Signal.
module counter(
input clk,
input reset,
output [127:0] counter_out,
output trig
);
reg trig=0;
reg [127:0] counter_out=0;
reg [7:0] temp=0;
always@(posedge clk)
begin
if(~reset)
begin
trig<=0;
counter_out<=0;
end
else
begin
counter_out<=counter_out+1;
temp<=temp+1;
if(temp==25)
begin
temp<=0;
trig<=~trig;
end
end
end
endmodule
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