hello guys,

I need some help with the port map in VHDL
 I have to port map a module to the top module something like

 port map ( a => b)

 the Problem is that b has been define in a record something like:

 type x is record 
 y : foo_in;
end record; 

and

 type foo_in is record
     b: std_logic;
end record; 

What I have done is create a Signal

 Signal t : x 

port map (
  a => t.b
) 

I don't think my port map is correct. What will be the proper way to do 
it.

Many thanks

Hi Miller,

Thanks for your Reply

a and b are both std_logic type  port signal. I have a Problem with the 
record in the middle.

I mean if I have to do

 port map (
   a => t.y.b;
) 

or

 port map(
   a => t.foo_in.b;
)

Thanks