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Forum: FPGA, VHDL & Verilog Record port map in VHDL


Author: New (Guest)
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hello guys,

I need some help with the port map in VHDL
 I have to port map a module to the top module something like
 port map ( a => b)
 the Problem is that b has been define in a record something like:
 type x is record 
 y : foo_in;
end record; 

and
 type foo_in is record
     b: std_logic;
end record; 

What I have done is create a Signal
 Signal t : x 

port map (
  a => t.b
) 

I don't think my port map is correct. What will be the proper way to do 
it.

Many thanks

Author: Lothar M. (lkmiller) (Moderator)
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New wrote:
> I don't think my port map is correct.
And whats the problem with it?
What error does what compiler report to you?
And please post a code snippet thats somehow compilable and simulable.

> What will be the proper way to do it.
What type is a?

Author: New (Guest)
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Hi Miller,

Thanks for your Reply

a and b are both std_logic type  port signal. I have a Problem with the 
record in the middle.

I mean if I have to do
 port map (
   a => t.y.b;
) 

or
 port map(
   a => t.foo_in.b;
)

Thanks

Author: Lothar M. (lkmiller) (Moderator)
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New wrote:
> I mean if I have to do
> port map (
>    a => t.y.b;
> )
> or
> port map(
>    a => t.foo_in.b;
> )
Give it a try!
The resulting process is called "learning"...

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