hello guys,

I need some help with the port map in VHDL
 I have to port map a module to the top module something like

1

 port map ( a => b)

 the Problem is that b has been define in a record something like:

1

 type x is record 

2

 y : foo_in;

3

end record;

and

1

 type foo_in is record

2

     b: std_logic;

3

end record;

What I have done is create a Signal

1

 Signal t : x 

2

port map (

3

  a => t.b

4

)

I don't think my port map is correct. What will be the proper way to do 
it.

Many thanks

Hi Miller,

Thanks for your Reply

a and b are both std_logic type  port signal. I have a Problem with the 
record in the middle.

I mean if I have to do

1

 port map (

2

   a => t.y.b;

3

)

or

1

 port map(

2

   a => t.foo_in.b;

3

)

Thanks