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Forum: FPGA, VHDL & Verilog ADC on DEO NANO not working


von chinmaye (Guest)


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Hello,

I am trying to get the ADC on the DEO Nano board working. I am dividing 
the 50 MHz clock to 1MHz and trying to read channel zero. But it doesn't 
seem to be working. Here is the code. The simulation works fine. But it 
is not showing up on the board.
I am trying to give the analog input through a POT and trying to get the 
output on LEDS. The LEDs simply do not glow for any input.

I have connected the IGO key to the dip switch. I am not sure if it 
works. Plz help.
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
4
// Engineer: 
5
// 
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// Create Date:    17:04:43 03/19/2018 
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// Design Name: 
8
// Module Name:    adc 
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// Project Name: 
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// Target Devices: 
11
// Tool versions: 
12
// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
17
// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ADC_CNTRL  (  
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          iRST,
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          CLK,
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          //iCLK_n,
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          iGO,
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          //iCH,
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          oLED,
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          oDIN,
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          oCS_n,
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          oSCLK,
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          iDOUT
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        );
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input        iRST;
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input        CLK;
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//input        iCLK_n;
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input        iGO;
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//input  [2:0]    iCH;
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output  [7:0]    oLED;
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//output [3:0] m_cont;
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output        oDIN;
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output        oCS_n;
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output        oSCLK;
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input        iDOUT;
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reg          data;
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reg          go_en;
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wire  [2:0]    ch_sel;
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reg          sclk;
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reg    [3:0]    cont;
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reg    [3:0]    m_cont;
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reg    [11:0]    adc_data;
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reg    [11:0]    led;
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//reg [2:0] iCH;
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reg iCLK = 0, iCLK_n = 1;
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parameter sys_clk = 50000000;  // 50 MHz system clock
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parameter clk_out = 1000000;  // 1 MHz clock output
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parameter max = sys_clk / (2*clk_out); // max-counter size
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reg [4:0]counter = 0; // 5-bit counter size
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always@(posedge CLK) begin
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  if (counter == max-1)
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    begin
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    counter <= 0;
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    iCLK <= ~iCLK;
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    iCLK_n <= ~iCLK_n;
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    end
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  else
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    begin
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    counter <= counter + 1'd1;
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    end
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  //Clk_out <= (counter == 5'd0);
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  end
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assign  oCS_n    =  ~go_en;
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assign  oSCLK    =  (go_en)? iCLK:1;
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assign  oDIN    =  data;
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//assign  ch_sel    =  iCH;
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assign  oLED    =  led;
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always@(posedge iGO or negedge iRST)
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begin
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  if(!iRST)
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    go_en  <=  0;
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  else
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  begin
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    if(iGO)
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      go_en  <=  1;
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  end
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end
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always@(posedge iCLK or negedge go_en)
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begin
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  if(!go_en)
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    cont  <=  0;
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  else
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  begin
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    if(iCLK)
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      cont  <=  cont + 1;
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  end
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end
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always@(posedge iCLK_n)
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begin
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  if(iCLK_n)
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    m_cont  <=  cont;
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end
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always@(posedge iCLK_n or negedge go_en)
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begin
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  if(!go_en)
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    data  <=  0;
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  else
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  begin
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    if(iCLK_n)
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    begin
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      if (cont == 2)
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        data  <=  0;
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      else if (cont == 3)
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        data  <=  0;
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      else if (cont == 4)
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        data  <=  0;
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      else
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        data  <=  0;
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    end
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  end
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end
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always@(posedge iCLK or negedge go_en)
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begin
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  if(!go_en)
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  begin
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    adc_data  <=  0;
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    led      <=  8'b00;
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  end
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  else
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  begin
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    if(iCLK)
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    begin
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      if (m_cont == 4)
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        adc_data[11]  <=  iDOUT;
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      else if (m_cont == 5)
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        adc_data[10]  <=  iDOUT;
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      else if (m_cont == 6)
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        adc_data[9]    <=  iDOUT;
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      else if (m_cont == 7)
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        adc_data[8]    <=  iDOUT;
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      else if (m_cont == 8)
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        adc_data[7]    <=  iDOUT;
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      else if (m_cont == 9)
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        adc_data[6]    <=  iDOUT;
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      else if (m_cont == 10)
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        adc_data[5]    <=  iDOUT;
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      else if (m_cont == 11)
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        adc_data[4]    <=  iDOUT;
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      else if (m_cont == 12)
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        adc_data[3]    <=  iDOUT;
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      else if (m_cont == 13)
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        adc_data[2]    <=  iDOUT;
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      else if (m_cont == 14)
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        adc_data[1]    <=  iDOUT;
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      else if (m_cont == 15)
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        adc_data[0]    <=  iDOUT;
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      else if (m_cont == 1)
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        led  <=  adc_data[11:4];
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    end
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  end
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end
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endmodule

von ElKo (Guest)


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Is the demo project working, which Terasic delivers on the CD? (and 
which you copied)

What do the LED show, if you assign "counter" to them?

Is this module your Toplevel? If so, did you change the pin assignments?

von Christian G. (Guest)


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Hi, a few days ago, I tried to get that same example project to run and 
also failed, it just did not work on the real hardware. To be honest I 
have no clue of verilog, so I ended up building my own adc_controller in 
vhdl and it turned out to be surprisingly easy once you read the adc 
datasheet, I used a PLL to create a clock double the speed of the adc 
clock I want than on the falling edge of the adc clock I push out the 
channel I want to read and on the rising edge of the adc clock I read 
the channel data back. It might not be by far the best solution but it 
works :
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library ieee;
2
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
4
5
entity adc_controller is
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  port
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  (
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    clk : in std_logic;    
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    reset : in std_logic;
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    output : out std_logic_vector(11 downto 0);
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    output_valid : out std_logic;
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    go : in std_logic;
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    ch_sel : in std_logic_vector(2 downto 0);
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    adc_clk : out std_logic;          -- The ADC clock (0.8 - 3.2 MHz) will be half the speed of clk !
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    adc_cs_n : out std_logic;
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    adc_sadr : out std_logic;
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    adc_dat : in std_logic
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  );
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end entity;
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architecture behavioural of adc_controller is
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  signal adc_data_out : std_logic_vector(15 downto 0) := (others => '0');
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  signal adc_data_in: std_logic_vector(15 downto 0) := (others => '0');
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  signal di_counter : natural range 0 to 15 := 0;
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  signal do_counter : natural range 0 to 15 := 0;
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  type tstate is (init, start, clock_low, clock_high, last_clock_high, stop);
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  signal state :tstate := init;
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begin
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  process
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  begin
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    wait until rising_edge(clk);
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    if (reset = '1') then
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      output <= (others => '0');
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      di_counter <= 15;
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      do_counter <= 15;
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      adc_data_in <= (others => '0');
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      adc_cs_n <= '1';
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      adc_clk <= '0';
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      output_valid <= '0';
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      state <= init;
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    else
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      case state is
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        when init =>
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          adc_clk <= '1';
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          adc_cs_n <= '1';
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          do_counter <= 15;
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          di_counter <= 15;
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          adc_sadr <= '0';
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          adc_data_in <= (others => '0');
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          adc_data_out <= "00" & ch_sel & "000" & "00000000";
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          output_valid <= '0';
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          if (go <= '1') then
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            state <= start;
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          else
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            state <= init;
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          end if;
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        when start =>
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          adc_cs_n <= '0';
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          state <= clock_low;
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        when clock_low =>
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          adc_clk <= '0';
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          adc_sadr <= adc_data_out(do_counter);
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          if (di_counter > 0) then
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            do_counter <= do_counter - 1;
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            state <= clock_high;
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          else
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            state <= last_clock_high;
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          end if;
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        when clock_high =>
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          adc_clk <= '1';
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          adc_sadr <= adc_data_out(do_counter);
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          adc_data_in(di_counter) <= adc_dat;
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          di_counter <= di_counter - 1;
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          state <= clock_low;
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        when last_clock_high =>
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          adc_clk <= '1';
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          adc_data_in(di_counter) <= adc_dat;
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          state <= stop;
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87
        when stop =>
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          adc_cs_n <= '1';
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          output <= adc_data_in(15 downto 4);
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          output_valid <= '1';
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          state <= init;
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        when others =>
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          adc_cs_n <= '1';
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          state <= init;
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      end case;      
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    end if;
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  end process;
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end behavioural;

top-level entity:
1
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity adc_test is
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  port
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  (
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    CLK_50 : in std_logic;
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    BTN_RST : in std_logic;
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    LED : out std_logic_vector(7 downto 0);
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    SWITCH : in std_logic_vector(3 downto 0);
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    ADC_CS : out std_logic;
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    ADC_DAT_IN : out std_logic;
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    ADC_DAT_OUT : in std_logic;
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    ADC_CLK : out std_logic
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  );
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end adc_test;
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architecture adc_test_arc of adc_test is
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  component pll_clock IS
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    PORT
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    (
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      inclk0    : IN STD_LOGIC  := '0';
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      c0    : OUT STD_LOGIC -- I used a 4MHz clock
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    );
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  END component;
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  component adc_controller is
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    port
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    (
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      clk : in std_logic;
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      reset : in std_logic;
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      output : out std_logic_vector(11 downto 0);
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      output_valid : out std_logic;
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      go : in std_logic;
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      ch_sel : in std_logic_vector(2 downto 0);
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      adc_clk : out std_logic;
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      adc_cs_n : out std_logic;
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      adc_sadr : out std_logic;
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      adc_dat : in std_logic
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    );
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  end component;
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  signal adc_controller_clk : std_logic := '0';
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  signal adc_data : std_logic_vector(11 downto 0) := (others => '0');
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  signal adc_data_valid : std_logic := '0';
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  signal adc_go : std_logic := '0';
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  signal rst_btn_sr : std_logic_vector(2 downto 0) := (others =>'0');
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  signal adc_reset : std_logic := '0';
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  signal rst_counter : natural := 0;
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  signal reset_me : std_logic := '0';
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begin
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  pll_clock_inst : pll_clock port map(
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    inclk0 => CLK_50,
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    c0 => adc_controller_clk
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  );
60
  
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  adc_controller_inst : adc_controller port map(
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    clk => adc_controller_clk,
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    reset => adc_reset,
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    output => adc_data,
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    output_valid => adc_data_valid,
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    go => adc_go,
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    ch_sel => SWITCH(2 downto 0),
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    adc_clk => ADC_CLK,
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    adc_cs_n => ADC_CS,
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    adc_sadr => ADC_DAT_IN,
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    adc_dat => ADC_DAT_OUT
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  );
73
  
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-- RESET button process
76
  reset_btn_proc : process
77
  begin
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    wait until rising_edge(CLK_50);
79
    rst_btn_sr <= rst_btn_sr(1 downto 0) & (NOT BTN_RST);
80
    if (rst_btn_sr = "111") then 
81
      reset_me <= '1'; 
82
    else 
83
      reset_me <= '0';
84
    end if;
85
  end process reset_btn_proc;
86
  
87
--RESET process  
88
  reset_proc :process
89
  begin
90
    wait until rising_edge(CLK_50);
91
    if (reset_me = '1') then
92
      rst_counter <= 100;
93
    end if;
94
    if (rst_counter > 0) then
95
      adc_reset <= '1';
96
      adc_go <= '0';
97
      rst_counter <= rst_counter - 1;
98
    else
99
      adc_reset <= '0';
100
      adc_go <= '1';
101
    end if;
102
  end process reset_proc;
103
  
104
-- LED process
105
  led_proc : process
106
  begin
107
    wait until rising_edge(CLK_50);
108
    if (adc_reset = '1') then
109
      LED <= (others => '0');
110
    else
111
      if (adc_data_valid = '1') then
112
        LED <= adc_data(7 downto 0);
113
      end if;
114
    end if;
115
  end process led_proc;
116
  
117
end adc_test_arc;

von Christian G. (Guest)


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...sorry, had still a few bugs in there...

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