EmbDev.net

Forum: FPGA, VHDL & Verilog Microprocessor Datapath FSM Controller


Author: Ed H. (howerj)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hello, I am trying to create a Finite State Machine to control the 
outputs specified in image 1. I have already created the Datapath module 
as shown in image 2. The instructions in image 1 are what is confusing 
me. I don't have a clear idea on what it wants. Any clarification would 
be much appreciated. I am also including the beginning of my FSM 
verilog.
module fsm(reset, clk, s, sel, ce, w, clr);
input clk,reset;
output clr;
output [2:0] w;
output [2:0] ce;
output [1:0] sel;
output [2:0] s;

reg clr;
reg [2:0] w;
reg [2:0] ce;
reg [1:0] sel;
reg [2:0] s;
reg [2:0] cs,ns;
parameter
s0=0;
s1=1;

always@(posedge clk or posedge reset)
begin 
    if (reset==1) cs<=s1;
    else cs<=ns;
end

always@ (cs or start)
begin
    case(cs)
    
    endcase
    end
  
  
always @ (cs)
begin
    case(cs)
   
    endcase
    end
endmodule


Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.