Hello, I am trying to create a Finite State Machine to control the outputs specified in image 1. I have already created the Datapath module as shown in image 2. The instructions in image 1 are what is confusing me. I don't have a clear idea on what it wants. Any clarification would be much appreciated. I am also including the beginning of my FSM verilog.
module fsm(reset, clk, s, sel, ce, w, clr); input clk,reset; output clr; output [2:0] w; output [2:0] ce; output [1:0] sel; output [2:0] s; reg clr; reg [2:0] w; reg [2:0] ce; reg [1:0] sel; reg [2:0] s; reg [2:0] cs,ns; parameter s0=0; s1=1; always@(posedge clk or posedge reset) begin if (reset==1) cs<=s1; else cs<=ns; end always@ (cs or start) begin case(cs) endcase end always @ (cs) begin case(cs) endcase end endmodule