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Forum: FPGA, VHDL & Verilog Microprocessor Datapath FSM Controller


von Ed H. (howerj)


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Hello, I am trying to create a Finite State Machine to control the 
outputs specified in image 1. I have already created the Datapath module 
as shown in image 2. The instructions in image 1 are what is confusing 
me. I don't have a clear idea on what it wants. Any clarification would 
be much appreciated. I am also including the beginning of my FSM 
verilog.
1
module fsm(reset, clk, s, sel, ce, w, clr);
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input clk,reset;
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output clr;
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output [2:0] w;
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output [2:0] ce;
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output [1:0] sel;
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output [2:0] s;
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reg clr;
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reg [2:0] w;
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reg [2:0] ce;
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reg [1:0] sel;
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reg [2:0] s;
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reg [2:0] cs,ns;
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parameter
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s0=0;
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s1=1;
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always@(posedge clk or posedge reset)
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begin 
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    if (reset==1) cs<=s1;
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    else cs<=ns;
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end
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always@ (cs or start)
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begin
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    case(cs)
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    endcase
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    end
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always @ (cs)
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begin
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    case(cs)
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    endcase
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    end
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endmodule

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