Hi Friends

I am trying to make a simple spi module with verilog. After I get the 
Enable signal, I want to send the 8 bit data in series.
I've never worked with a verilog before.
I wrote a simple code but I do not know how to generate the clock 
signal.

this is my Code;

`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 03/31/2017 at 15:12
// Component: ParalelToSerial
module ParalelToSerial (
  output  Busy,
  output  Clkout,
  output  Dout,
  input   Clkin,
  input  [7:0] Data,
  input   En
);

//`#start body` -- edit after this line, do not edit this line
    reg busy;
    reg dout;
    reg clkout;   
    reg [3:0]cnt_spi;
    reg clk_count;
   
    assign Busy = busy;
    assign Dout = dout;
    assign Clkout = clkout;
  
    always @ (negedge Clkin)
    begin
       if(En == 1'b1 && busy == 1'b0)
       begin         
         clkout=1'b0;
         dout=Data[cnt_spi];
         cnt_spi = cnt_spi + 1;       
       end
       
       if(cnt_spi == 8)
         busy=1'b0;
       begin 
       
       end
    end
    
//`#end` -- edit above this line, do not edit this line
endmodule

I will be glad if you help me. I'm just looking for a very simple 
example of spi.

Ferhat Y. wrote:
> I've never worked with a verilog before.
So, why not starting with a flashing LED?

> I am trying to make a simple spi module with verilog. After I get the
> Enable signal, I want to send the 8 bit data in series.
So you want to do an SPI master. For me the SS is missing there...

> I wrote a simple code but I do not know how to generate the clock signal.
You must
1. you must generate a scaled down SCLK "clock" signal out of the FPGA 
clock (which is usually round 50MHz)
2. you must generate a SS slaveselect signal and activate it before 
start of transaction
3. you must shift the data bit by bit on the MOSI line according to the 
phse of the SCLK
5. you must be aware that the SCLK is a simple output signal and NO 
clock(!!!)
4. you must set up a test bench to verify the behaviour of the whole 
thing

But if I were you I would start with the LED and simulate it before 
going on real hardware. And be aware: the simulator is the HDL debugger!

Hi @Ikmiller

Thank you for the reply.

Before starting this application, I did flashing LED.

I'm testing it in real hardware. it works :)
    always @ (posedge Clkin)  //1Khz Clock İnput
    begin
      if(counter== 500)
      begin
        counter=0;
        clkout = ~clkout;
      end
    end

Now, I'm working on the PSoC devices. PSoCs have microcontroller and 
PGA. PGA is programmed with verilog like fpga. I don't need SS in my 
application because, I'm driving P10 LED panel, This panels only have 
DATAIN and CLOCKIN inputs.

PSoC itself is doing frequency division. I only determine the clock 
frequency.

PSoCs are being designed with blocks. (my design in the attachment)
Now I need to write the contents of the Parallel_to_Serial module with 
verilog.

I've sent a bit of bits to send
dout=Data[cnt_spi];
I just need to generate the SCLK signal.And a little control. (Busy 
signal vs)

Ferhat Y. wrote:
> I'm testing it in real hardware. it works :)
Do a simulation on it. Just to learn how a simulation is done. You will 
find out, that there is a problem in your design: with a 1kHz clock you 
will not get the desired 1Hz flashing...

> always @ (posedge Clkin)  //1Khz Clock İnput
Run the FPGA on a much higher clock. And from there generate clock 
enables for slower timings.

> PSoCs are being designed with blocks. (my design in the attachment)
> Now I need to write the contents of the Parallel_to_Serial module with
> verilog.
Its just a parallel loaded shift register.
> I've sent a bit of bits to send dout=Data[cnt_spi];  I just need to
> generate the SCLK signal.
When looking at the picture: you already have a clock...

> And a little control. (Busy signal vs)
And it will be a good idea to add a sync signal (in SPI its called SS 
slaveselect) to the output.

This example is with automatic shiftout.

IIRC, it was not tested yet on real hardware. Only in simulator.

Just found a more simple version. spi_master2.

Syntax
$dumpfile("filename.vcd")
$dumpvar //dumps all variables in the design.
$dumpvar(1, top) //dumps all the variables in module top and below, but 
not modules instantiated in top.
$dumpvar(2, top) //dumps all the variables in module top and 1 level 
below.
$dumpvar(n, top) //dumps all the variables in module top and n-1 levels 
below.
$dumpvar(0, top) // dumps all the variables in module top and all level 
below.
$dumpon // initiates the dump.
$dumpoff // stop dumping

All the best :)
VLSI Training at CETPA