I have used Xilinx core generator to synthesize a bram with width of 16
bit and depth of 80k, resulting a 17-bit address. Let's call them
bram_data, and bram_addr.
I am connecting the bram to PLB bus which has 32-bit address
(Bus2IP_Addr) and 32-bit data (Bus2IP_Data).
I am not sure how to connect those two together since I don't understand
if the address is not at the 32-bit boundary:
(1) Does Bus2IP_Addr contains the requested address (0x2 for example),
or the closest 32-bit boundary (0x0 for example).
(2) Does Bus2IP_Data contains the data at 0x2, or data at 0x0 ?
I have tried all the combinations I could think of but nothing seems to
thank you very much.