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Forum: FPGA, VHDL & Verilog One big module vs multiple small?


Author: Mark L. (markl)
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Hi,

I perfectly understand that multiple modules help with human interaction 
(readbility, productivity, code updating..).

It is the same as in C++.

But in Verilog, is there anything (I mean technically, or the standard) 
preventing me from having a huge module, with all the contrained IO 
ports declared as input/ouput, functions and all the always blocks doing 
their -very different- thing?

Are synthesis tools more confortable with multiple small modules vs one 
big? Should be the same to me.

Thanks for your opinion,

[Digression On] I finally wrote multiple synthesizable codes and I am 
happy. I just had to change my mind. And for this, thanks for the 
help.[Digression Off]

Author: Cle (Guest)
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I can't think of any technical reason that would require you to split 
bigger modules.

Also just wanted to add the two of the most important points for smaller 
design: Testing and reusability.

Smaller modules are easier and better testable and then you can combine 
them in an easier way for bigger blocks. As we build hardware the basic 
components will often be very similar and you can build standard blocks 
with a standard set that fits your workflow very easily.

Author: Mark L. (markl)
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Cle,
Thanks for your input.
You are right on every point you made.

As for the big module,  maybe differences will emerge from one 
synthesizer to another though.
Time will tell

Author: Luke Wren (Guest)
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Another point is that, when you get down to optimising your design for 
area/clock period/(insert your metric here), it is a lot easier to get 
to the root of your problems if your design is modular.

Not to mention that synthesising one small module is much faster than 
the entire design! Getting fast feedback from your synthesis tool is 
useful for optimisation.

Also, as the others said, testability. Testing (verification) is about 
2/3rds of the work in getting a design into production, i.e. twice as 
much as actually writing your RTL. Good luck doing unit testing with one 
huge module :-)

Author: S. R. (svenska)
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Keep in mind that while having lots of smaller modules allows you to do 
easy unit-testing, additional complexity will appear due to the 
connections.

The problem complexity must exist somewhere. If not within the modules, 
then between them.

Author: Mark L. (markl)
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Exact. Lot of eye-opening answers, thank you so much!

Author: C. A. Rotwang (Guest)
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synthesis tool does hierarchy removal aka "design flattening", so it's 
no need to do this by hand.

https://www.xilinx.com/support/documentation/sw_ma...

Author: Mark L. (markl)
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Thanks C.A. ! Lattice does that too with the diamond programmer 
apparently

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