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Forum: FPGA, VHDL & Verilog Post-synthesis simulation, Quartus and Modelsim-Altera


Author: Reza M. Shahshahani (Company: SBU) (shahshahani86)
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Dear all
I have synthesized my VHDL-coded design in Quartus v17 and have the 
netlist (vho) file. But the problem is that after synthesis, my design 
data ports in the resulting netlist file has changed from signed to 
std_logic_vector. What's the problem? How can I resolve this issue?
Thanks
Reza

Author: Lothar Miller (lkmiller) (Moderator)
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Reza M. S. wrote:
> How can I resolve this issue?
Don't do a Post-Whatever-Simulation. It's useless. Perform a behavioural 
simulation and use proper constraints. That's all you need.

> How can I resolve this issue?
Use std_logic in your ports. To use std_logic in ports is an unofficial 
industry standard.

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