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Forum: FPGA, VHDL & Verilog initializing oled display using vhdl


Author: Alex H. (alex_hanson)
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HI!

I'm trying to use a LCD project in my own project but i dont really 
understand this project especially with the counters and timers

I have uploaded the file and the datasheet for the oled_display!

I hope I can get a clarification for this

Author: Lothar M. (lkmiller) (Moderator)
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Alex H. wrote:
> i dont really understand this project especially with the counters and
> timers
What about doing a simulation of that design and analyze its behaviour? 
The only thing your testbench must supply is a clock and the reset.

By looking at the code i see something like that:
    if rising_edge(clk) and cnt < 1000000 then
      cnt <= cnt + 1;
    elsif rising_edge(clk) and cnt = 1000000 then
And by seeing that I urge you to take that display control code more as 
a "how-not-to" example...

> I have uploaded the file and the datasheet for the oled_display!
Thats obviously a straight forward HD44780 compatible interface. You can 
find lots of code for controlling such displays.
By comparing the simulation results to the data sheet I see some 
potential to improve timings...


BTW: when attaching *.vhdl files instead of *.txt files some kind of 
magic named "syntax highlighting" happens.

: Edited by Moderator
Author: Theor (Guest)
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Please ask specific questions.

Generic questions like yours will lead in consequence either to us doing 
it for you or explaining you the whole thing. This is not considered the 
purpose of that forum.

Thank you.

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