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Forum: FPGA, VHDL & Verilog Verilog For Counter: How to store 32 bit counter values as 4 8-bit registers ?


Author: Saraswathy S. (saras015)
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Hi,

  I am new to HDL language. I have written and compile basic Counter 
Verilog code. But i need store 32 bit counter values as 4 8-bit 
registers ? Please someone help me


module counter
#(parameter WIDTH=8)
(
  input clk, enable, rst_n,
  output reg [WIDTH-1:0] count
);

  always @ (posedge clk or negedge rst_n)
  begin
    if (~rst_n)
      count <= 0;
    else if (enable == 1'b1)
      count <= count + 1;
  end
endmodule

Author: Lothar M. (lkmiller) (Moderator)
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Saraswathy S. wrote:
> 32 bit counter
There is no 32 bit counter in that design.

> But i need store 32 bit counter values as 4 8-bit registers ?
Where do you need to store the counter? Whats your actual problem? Whats 
the original text of your exercise?

Author: Saraswathy S. (saras015)
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Thanks for your response.

Sorry. Trying for 32-bit counter
#(parameter WIDTH=32)
.

I need to store like below
output reg [7:0]  Data_out_0,
      output reg [7:0]  Data_out_1,
      output reg [7:0]  Data_out_2,
      output reg [7:0]  Data_out_3,
.

 Any logic in Verilog, like switch cases.

Author: Vancouver (Guest)
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Define a local 32bit counter register and connect your Data_out_x to the 
corresponding bytes of this register. Use 'logic' or 'wire' instead of 
'reg' type for the outputs.

Author: Saraswathy S. (saras015)
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Then how should i include my counter logic.

 module counter
        #(parameter WIDTH=32)
        (
        input clk, enable, rst_n,
        output reg [WIDTH-1:0] count
         );
         output wire [7:0]  Data_out_0,
        output wire [7:0]  Data_out_1,
        output wire [7:0]  Data_out_2,
        output wire [7:0]  Data_out_3, 

 Please tell me how to complete this process

Author: Andy (Guest)
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Make the 32bit counter as in your first post, and then assign the right 
portion of the counter to the output byte 0..3. Here the second byte, 
the others are up to you:
   ...
   assign Data_out_1 = count[15:8];
   ...

You don't need to declare the count reg as output, just make it a local 
register.

Author: Saraswathy S. (saras015)
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Please check now whether my code is right.
      module counter
      (
        input clk, enable, rst_n,
        output [31:0] count,
      );
        output wire [7:0]  Data_out_0;
        output wire [7:0]  Data_out_1;
        output wire [7:0]  Data_out_2;
        output wire [7:0]  Data_out_3;

        assign Data_out_0 = count[7:0];
        assign Data_out_1 = count[15:8];
        assign Data_out_2 = count[23:16];
        assign Data_out_3 = count[31:24];

        always @ (posedge clk or negedge rst_n)
        begin
        if (~rst_n)
        count <= 0;
        else if (enable == 1'b1)
        count <= count + 1;
        end
        endmodule

Author: Mark L. (markl)
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I started verilog two weeks ago, so my example may not be the best.
Actually, if it is wrong or could be improved, PLEASE suggest.

The code is modified to emphasize the fact that it does what you need. 
The counter is not starting at 0, nor is it reset, but that is on 
purpose. Read the comments and change whatever you need.

This is what I would do:
module top();
  wire [7:0] my_reg1;
  wire [7:0] my_reg2;
  wire [7:0] my_reg3;
  wire [7:0] my_reg4;
  wire update;
  reg clk= 0,enable = 1 ,rst_n = 1;

  counter count(clk,enable,rst_n,update,my_reg1,my_reg2,my_reg3,my_reg4);

  always @ (clk)// simplified clock
    begin
      #1 clk <= ~clk;
      $display("CLOCK");
    end

  always @( update) // replace with the store logic
/* actually, maybe we should react to event on enable but I decided otherwise for this contrived example*/
    begin
      if (update == 1)
        begin
          $display("-->> STORE THIS %h %h %h %h",my_reg1, my_reg2, my_reg3, my_reg4);
        end
    end

  initial
    begin
      #20 $display("FINAL PHASE");
      #1 $display("%d %d %d %d",my_reg1, my_reg2, my_reg3, my_reg4);
      #1 $finish;
    end

endmodule

module counter
  #(parameter WIDTH=32, WIDTH2=8)
  (
    input clk, enable, rst_n, 
    output wire update,
    output wire [WIDTH2-1:0] my_reg1,
    output wire [WIDTH2-1:0] my_reg2,
    output wire [WIDTH2-1:0] my_reg3,
    output wire [WIDTH2-1:0] my_reg4
  );

  /* Could have been the cleaner "reg [7:0] my_arr[4];" but it requires that you change the output and references accordingly
  */
  reg [WIDTH2-1:0] lmy_reg1;
  reg [WIDTH2-1:0] lmy_reg2;
  reg [WIDTH2-1:0] lmy_reg3;
  reg [WIDTH2-1:0] lmy_reg4;

  reg [WIDTH-1:0] count = 32'h11_22_33_44; /* force it at an arbitrary value. Deliberately ignoring rst instance. Modify it to your taste.*/
  reg lupdate = 0;

  assign my_reg1 = lmy_reg1;
  assign my_reg2 = lmy_reg2;
  assign my_reg3 = lmy_reg3;
  assign my_reg4 = lmy_reg4;
  assign update = lupdate;

  always @ (posedge clk or negedge rst_n)
    begin
      lupdate <= 0;
      if (~rst_n)
        begin
          $display("reset on");
          count <= 0;
        end
      else if (enable == 1'b1) // in production code "enable" should drive the always block in top module, not the "update" variable.
        begin
          $display("count add 1");

          count <= count + 32'h11_11_11_11; // replace it with
          lmy_reg1 <= count[31:24];
          lmy_reg2 <= count[23:16];
          lmy_reg3 <= count[15:8];
          lmy_reg4 <= count[7:0];
          lupdate <= 1;
        end
    end

endmodule

Again, I am a beginner too in Verilog.

: Edited by User
Author: Andy (Guest)
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Saraswathy S. wrote:
> Please check now whether my code is right.

Not quite. The Synthesis tool will give you a few errors.

You need to declare all input and output ports inside the first 
parenthesis section.
You also have the Data_out_0..3 as output ports, so they have to go 
there.

If you don't need to access the count from outside the module, declare 
it after the parenthesis as follows:
module counter
   (
      ...    // in-out ports here
   );
   reg [31:0] count;    // a register used only inside the module 
   ...

Author: Marcus H. (mharnisch)
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You could check if your tool supports SystemVerilog and change the port 
declaration like this:
output reg [WIDTH/8-1:0][7:0] count

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