Forum: FPGA, VHDL & Verilog is at left hand side of signal assignment statement.

Author: Wilson Torres (Company: ECCI University) (will_t)
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hello !, I have a small problem with this code, I have 4 parallel inputs 
coming from the FPGA switches. what I try to do is something similar to 
a shift register, an FPGA button will simulate a clock signal, when I 
press it for the first time, the data that enters parallel must make a 
shift, example (if you enter "0101", when pressing the button the first 
time a bit must be sent to the left, that is to say "1010", when it is 
pressed for the second time "0101" and so on). For this I used ROL, but 
I do not know how to do the increments of the ROL, I tried to use a beat 
counter of the clock button but it gives me the following error:

Line 31. Variable 'cnt' cnt is at left hand side of signal assignment 

Use 4 LEDs to see the Original input (RD_out) and other 4 LEDs (RD_out2) 
to see the ROLE in the data.

Thank you in advance for your help,

Best regards!

Author: Lothar Miller (lkmiller) (Moderator)
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Wilson T. wrote:
> an FPGA button will simulate a clock signal
Hopefully it's debounced!

> For this I used ROL, but I do not know how to do the increments
What's the hardware you are describing with this VH-Description-L 
code? Do you have a sketch of that hardware on paper? Or at least a 
picture of that hardware in mind?
Or do you try to "program" and use some kind of VH-Programming-Language?

A PISO usually has only 1 serial output. And this could be selected with 
your counter and a multiplexer:

But be aware that cnt runs out of the borders of that array very fast. 
You must reset cnt to 0 when it reaches the top border of the array.

Assignments to variables are done with :=
I suppose to use signals.

All together I would do it much like this way by adding an output which 
is high at the first bit of the serial protcol:
library IEEE;

entity convertparal_serie is 

  port (inDCBA: in  std_logic_vector (3 downto 0);  -- 4 inputs
        reloj:  in  std_logic;                      -- some kind of clock
        outSER: out std_logic;                      -- serial output
        bit0:   out std_logic);                     -- marker for first bit

end convertparalelo_serie;

architecture Behavioral of convertparal_serie is

  signal cnt: integer := 0;


  -- cycling counter from 0 to 3 
  process (reloj) begin
    if reloj'event and reloj='1' then
      if cnt=3 then cnt <= 0
      else          cnt <= cnt + 1;
      end if;
    end if;
  end process;

  -- multiplex the parallel inputs to the serial output
  outSER <= inDCBA(cnt);

  -- signal the outer component that bit 0 is transmitted
  bit0 <= '1' when cnt=0 else '0';

end Behavioral;

: Edited by Moderator


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