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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
VHDL process issue : double execution Sacha 17
Network on chip implementation in FPGA Bala Krishnan 2
Verilog state machine query Kenny Millar 9
DE0_NANO_ADC jeorges FrenchRivera 4
function "to_integer" Mira Miyou 9
Digital to analog converter DAC and FPGA issam sassi 0
Progam in VHDL for a ttl finder Jose Maria 0
Verilog FPGA Compatibility Charan Mehta 2
32-to-1 multiplexer VHDL code simplification Zoltan Preiner 2
4-Bit Structural Adder using port map Jay JA 4
VHDL Counter Problem (Please help) Icy Snow 2
warning when synthesis afsoon 2
Error when using with-select-when in VHDL Ayush Khemka 3
Parallel MAC unit based on modified booth algorithm Jithin Smmb 1
VHDL MODEL FOR SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT Naija Coding 3
modified nodal analysis Mohammad Mothermohammad 2
Basic memory unit help Omar Rashad 2
USB interface Lukas 1e+007 8
Simple 16 bit Arithmetic Unit Omar Rashad 3
Xilinx 8.1 & Xilinx 14.7 Version will not compile my design Lewis Mbuthia 3
FPGA # Processor Itron Xtron 3
16 bit PISO register Omar Rashad 18
Newbie question about 'inout' Kenny Millar 7
Two digit BCD adder Yhx Yhx 2
locked 16 bit serial multiplier Omar 13
multiplier a matrice Mohammad Mothermohammad 3
mux using system generator REKHA V P 2
accurate counter Mohammad Mothermohammad 3
Choice of Hardware Sunayana C. 0
locked VHDL code help (beginner level) Omar 6
MACHXO2 - accessing Wishbone EFB i2c from Verilog? Kenny Millar 6
Using the Xilinx ISE Design Suite 14.7 version Juan 6
RS-232 communication with XUPV5-LX110T evaluation platform (Xilinx) issam sassi 0
Audio Interfacing with FPGA Jack Born 12
Algorithm for x/63 and x/127 Nikolaos Kavvadias 13
Binning + Pipeline, How to do it, please? Enrique Perez 7
Display 640x480 Nexys 3 board sketchy 8
Lattice MACHXO2 EFB i2c. No activity in simulation Antony Mathew 6
SPI works sometimes Joshua Vasquez 6
VHDL code to implement a SATA disk controller on a Virtex 5 FPGA Sunayana C. 5
Using PLL in the code Kevin 0
Best FPGA setup for AES encryption Hendrik Türk 0
Addressing many registers SparkyT 13
cheap FPGA kit + camera OV7670 ? franofcholet 1
Issue with inout ports bob 1
Unit testing- too much maintenance overhead? R L 3
Communication system: Interleaver Rob Griffin 8
Calculate Sum of (z[n])^2 in VHDL Eric Thompson 4
4.3" LCD Touch Panel LTM Dlitwp S. 5
Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification Jay 1
Serial signal in DAC angelo 4