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Forum: FPGA, VHDL & Verilog 4-Bit Structural Adder using port map


von Jay J. (jboss10)


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I have this 4-bit adder that I'm having trouble compiling.
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--This snippet of code was given to us. From here, we needed to create the structural design with the correct port mapping. 
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entity adder is
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                port       (Ain,Bin,Cin : in std_logic;
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                            Sout,Cout : out std_logic);
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end entity adder;
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architecture adder_arch of adder is
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     begin
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               Sout <= Ain xor Bin xor Cin;
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               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);
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end architecture adder_arch;
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--End of given code
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--Start of my code
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entity FourBit_Adder is 
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 port (          a  : in  std_logic_vector (3 downto 0);
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    b  : in  std_logic_vector(3 downto 0);
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    c_in  : in  std_logic;
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    c_out  : out  std_logic;
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    sum  : out  std_logic_vector(3 downto 0)
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    );
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end FourBit_Adder;
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architecture FourBit_Adder_arch of FourBit_Adder is
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 signal S: std_logic_vector(2 downto 0);
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 component adder is
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     port(
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       Ain, Bin, Cin: in std_logic;
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       Sout, Cout : out std_logic);
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end component;
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begin
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FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));
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FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));
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FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));
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FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          
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end architecture FourBit_Adder_arch;

When compiling, I'm getting the error message "std_logic_vector" is used 
but not declared. Not sure what's up. I appreciate your feedback.
I'm using Altera's Quartus II software version 13.1

von Lothar M. (lkmiller) (Moderator)


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Justin JB wrote:
> --This snippet of code was given to us. From here, we needed to create
> the structural design with the correct port mapping.
In both cases something is missing before the keyword "entity". Just 
have a look how every VHDL description starts...

> --End of given code
Also after this line something is missing. Every VHDL module has the 
same structure:
- libraries/packages
- entity
- architecture
All those keywords must occur in a "usual" VHDL module. Just have a 
look for simple samples about components or type the keywords "vhdl 
structural adder" into google. You will find lots of hits...

von Jay J. (jboss10)


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My mistake, I just forgot to post with the libraries included. I don't 
need the library statement twice in one VHDL code, correct? You said in 
both cases something is missing before entity unless you just were 
referring to it once.
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library ieee;
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use ieee.std_logic_1164.all; 
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use ieee.std_logic_unsigned.all;
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entity adder is
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                port       (Ain,Bin,Cin : in std_logic;
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                           Sout,Cout : out std_logic);
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end entity adder;
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architecture adder_arch of adder is
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     begin
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          Sout <= Ain xor Bin xor Cin;
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               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);
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end architecture adder_arch;
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entity FourBit_Adder is 
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 port (  a    : in  std_logic_vector(3 downto 0);
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      b    : in  std_logic_vector(3 downto 0);
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      c_in  : in  std_logic;
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      c_out  : out  std_logic;
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      sum  : out  std_logic_vector(3 downto 0)
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    );
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end FourBit_Adder;
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architecture FourBit_Adder_arch of FourBit_Adder is
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 signal S: std_logic_vector(2 downto 0);
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 component adder is
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     port(
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       Ain, Bin, Cin: in std_logic;
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       Sout, Cout : out std_logic);
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end component;
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begin
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        FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));
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        FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));
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        FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));
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        FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          
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end architecture FourBit_Adder_arch;

von Jay J. (jboss10)


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@Lothar Miller

I figured it out! Thank you for your help! I did forget to place the 
library in the correct spot and my port mapping was incorrect.
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--Revised edition
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library ieee;
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use ieee.std_logic_1164.all; 
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use ieee.std_logic_unsigned.all;
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entity adder is
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                port       (Ain,Bin,Cin : in std_logic;
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                           Sout,Cout : out std_logic);
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end entity adder;
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architecture adder_arch of adder is
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     begin
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          Sout <= Ain xor Bin xor Cin;
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               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);
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end architecture adder_arch;
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library ieee;
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use ieee.std_logic_1164.all; 
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entity FourBit_Adder is 
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 port (  c_in    : in  std_logic;
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      a  : in  std_logic_vector(3 downto 0);
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      b  : in  std_logic_vector (3 downto 0);
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      c_out  : out  std_logic;
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      sum  : out  std_logic_vector(3 downto 0)
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    );
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end FourBit_Adder;
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architecture FourBit_Adder_arch of FourBit_Adder is
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 component adder is
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     port(
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       Ain, Bin, Cin: in std_logic;
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       Sout, Cout : out std_logic);
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end component;
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 signal S: std_logic_vector(2 downto 0);
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begin
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        FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => S(0),Sout => sum(0));
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        FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));
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        FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));
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        FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          
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end architecture FourBit_Adder_arch;

von Lothar M. (lkmiller) (Moderator)


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Justin JB wrote:
> Thank you for your help!
Welcome!

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