I have this 4-bit adder that I'm having trouble compiling.
--This snippet of code was given to us. From here, we needed to create the structural design with the correct port mapping. entity adder isport (Ain,Bin,Cin : instd_logic;
Sout,Cout : outstd_logic);
endentity adder;
architecture adder_arch of adder isbegin
Sout <= Ain xor Bin xor Cin;
Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);
endarchitecture adder_arch;
--End of given code--Start of my codeentity FourBit_Adder isport ( a : instd_logic_vector (3downto0);
b : instd_logic_vector(3downto0);
c_in : instd_logic;
c_out : outstd_logic;
sum : outstd_logic_vector(3downto0)
);
end FourBit_Adder;
architecture FourBit_Adder_arch of FourBit_Adder issignal S: std_logic_vector(2downto0);
component adder isport(
Ain, Bin, Cin: instd_logic;
Sout, Cout : outstd_logic);
endcomponent;
begin
FULLA0: adder portmap ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));
FULLA1: adder portmap ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));
FULLA2: adder portmap ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));
FULLA3: adder portmap ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));
endarchitecture FourBit_Adder_arch;
When compiling, I'm getting the error message "std_logic_vector" is used
but not declared. Not sure what's up. I appreciate your feedback.
I'm using Altera's Quartus II software version 13.1
Justin JB wrote:> --This snippet of code was given to us. From here, we needed to create> the structural design with the correct port mapping.
In both cases something is missing before the keyword "entity". Just
have a look how every VHDL description starts...
> --End of given code
Also after this line something is missing. Every VHDL module has the
same structure:
- libraries/packages
- entity
- architecture
All those keywords must occur in a "usual" VHDL module. Just have a
look for simple samples about components or type the keywords "vhdl
structural adder" into google. You will find lots of hits...
My mistake, I just forgot to post with the libraries included. I don't
need the library statement twice in one VHDL code, correct? You said in
both cases something is missing before entity unless you just were
referring to it once.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder isport (Ain,Bin,Cin : instd_logic;
Sout,Cout : outstd_logic);
endentity adder;
architecture adder_arch of adder isbegin
Sout <= Ain xor Bin xor Cin;
Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);
endarchitecture adder_arch;
entity FourBit_Adder isport ( a : instd_logic_vector(3downto0);
b : instd_logic_vector(3downto0);
c_in : instd_logic;
c_out : outstd_logic;
sum : outstd_logic_vector(3downto0)
);
end FourBit_Adder;
architecture FourBit_Adder_arch of FourBit_Adder issignal S: std_logic_vector(2downto0);
component adder isport(
Ain, Bin, Cin: instd_logic;
Sout, Cout : outstd_logic);
endcomponent;
begin
FULLA0: adder portmap ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));
FULLA1: adder portmap ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));
FULLA2: adder portmap ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));
FULLA3: adder portmap ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));
endarchitecture FourBit_Adder_arch;