4-Bit Structural Adder using port map

Jay J. OP #3872074
Rate this post
• ▲ useful
▼ not useful 
I have this 4-bit adder that I'm having trouble compiling.

1
 

2
--This snippet of code was given to us. From here, we needed to create the structural design with the correct port mapping. 

3
entity adder is

4
                port       (Ain,Bin,Cin : in std_logic;

5
                            Sout,Cout : out std_logic);

6
end entity adder;

7
 

8
architecture adder_arch of adder is

9
     begin

10
               Sout <= Ain xor Bin xor Cin;

11
               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);

12
end architecture adder_arch;

13
--End of given code

14


15
--Start of my code

16
entity FourBit_Adder is 

17


18
 port (          a  : in  std_logic_vector (3 downto 0);

19
    b  : in  std_logic_vector(3 downto 0);

20
    c_in  : in  std_logic;

21
    c_out  : out  std_logic;

22
    sum  : out  std_logic_vector(3 downto 0)

23
    );

24
  

25
end FourBit_Adder;

26


27
architecture FourBit_Adder_arch of FourBit_Adder is

28


29
 signal S: std_logic_vector(2 downto 0);

30


31
 

32
 component adder is

33
     port(

34
       Ain, Bin, Cin: in std_logic;

35
       Sout, Cout : out std_logic);

36
  

37
end component;

38
  

39
 

40
  

41
begin

42


43
FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));

44
FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));

45
FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));

46
FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          

47
                             

48
end architecture FourBit_Adder_arch;


When compiling, I'm getting the error message "std_logic_vector" is used 
but not declared. Not sure what's up. I appreciate your feedback.
I'm using Altera's Quartus II software version 13.1
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #3872084
Rate this post
• ▲ useful
▼ not useful 
Justin JB wrote:
> --This snippet of code was given to us. From here, we needed to create
> the structural design with the correct port mapping.
In both cases something is missing before the keyword "entity". Just 
have a look how every VHDL description starts...

> --End of given code
Also after this line something is missing. Every VHDL module has the 
same structure:
- libraries/packages
- entity
- architecture
All those keywords must occur in a "usual" VHDL module. Just have a 
look for simple samples about components or type the keywords "vhdl 
structural adder" into google. You will find lots of hits...
Reply Quote Edit Delete Report post
Jay J. OP #3872725
Rate this post
• ▲ useful
▼ not useful 
My mistake, I just forgot to post with the libraries included. I don't 
need the library statement twice in one VHDL code, correct? You said in 
both cases something is missing before entity unless you just were 
referring to it once.

1
library ieee;

2
use ieee.std_logic_1164.all; 

3
use ieee.std_logic_unsigned.all;

4


5
entity adder is

6
                port       (Ain,Bin,Cin : in std_logic;

7
                           Sout,Cout : out std_logic);

8
end entity adder;

9
 

10
architecture adder_arch of adder is

11
     begin

12
          Sout <= Ain xor Bin xor Cin;

13
               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);

14
        

15
end architecture adder_arch;

16


17


18
entity FourBit_Adder is 

19


20
 port (  a    : in  std_logic_vector(3 downto 0);

21
      b    : in  std_logic_vector(3 downto 0);

22
      c_in  : in  std_logic;

23
      c_out  : out  std_logic;

24
      sum  : out  std_logic_vector(3 downto 0)

25
    );

26
  

27
end FourBit_Adder;

28


29
architecture FourBit_Adder_arch of FourBit_Adder is

30


31
 signal S: std_logic_vector(2 downto 0);

32


33
 

34
 component adder is

35
     port(

36
       Ain, Bin, Cin: in std_logic;

37
       Sout, Cout : out std_logic);

38
  

39
end component;

40
  

41
 

42
  

43
begin

44


45
        FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => c_in,Sout => sum(0));

46
        FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));

47
        FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));

48
        FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          

49
                             

50
end architecture FourBit_Adder_arch;
Reply Quote Edit Delete Report post
Jay J. OP #3872749
Rate this post
• ▲ useful
▼ not useful 
@Lothar Miller

I figured it out! Thank you for your help! I did forget to place the 
library in the correct spot and my port mapping was incorrect.

1
--Revised edition

2
library ieee;

3
use ieee.std_logic_1164.all; 

4
use ieee.std_logic_unsigned.all;

5


6
entity adder is

7
                port       (Ain,Bin,Cin : in std_logic;

8
                           Sout,Cout : out std_logic);

9
end entity adder;

10
 

11
architecture adder_arch of adder is

12
     begin

13
          Sout <= Ain xor Bin xor Cin;

14
               Cout <= (Bin and Cin) or (Ain and Bin) or (Ain and Cin);

15
        

16
end architecture adder_arch;

17


18
library ieee;

19
use ieee.std_logic_1164.all; 

20


21
entity FourBit_Adder is 

22


23
 port (  c_in    : in  std_logic;

24
      a  : in  std_logic_vector(3 downto 0);

25
      b  : in  std_logic_vector (3 downto 0);

26
      c_out  : out  std_logic;

27
      sum  : out  std_logic_vector(3 downto 0)

28
    );

29
  

30
end FourBit_Adder;

31


32
architecture FourBit_Adder_arch of FourBit_Adder is

33


34
 

35
 component adder is

36
     port(

37
       Ain, Bin, Cin: in std_logic;

38
       Sout, Cout : out std_logic);

39
  

40
end component;

41
  

42
 signal S: std_logic_vector(2 downto 0);

43
  

44
begin

45


46
        FULLA0: adder port map ( Ain => a(0),Bin => b(0),Cin => c_in,Cout => S(0),Sout => sum(0));

47
        FULLA1: adder port map ( Ain => a(1),Bin => b(1),Cin => S(0),Cout => S(1),Sout => sum(1));

48
        FULLA2: adder port map ( Ain => a(2),Bin => b(2),Cin => S(1),Cout => S(2),Sout => sum(2));

49
        FULLA3: adder port map ( Ain => a(3),Bin => b(3),Cin => S(2),Cout => c_out,Sout => sum(3));          

50
                             

51
end architecture FourBit_Adder_arch;
Reply Quote Edit Delete Report post
Watch this topic

Reply

Please log in before posting.

Existing account

or

Log in with Google account

No account?

Registration is free and takes only a minute.

Register now