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Forum: FPGA, VHDL & Verilog Binning + Pipeline, How to do it, please?


Author: Enrique Perez (flote21)
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Hello guys!

I need to make a binning of the pixel output of a sensor. The binning 
process is based on adding 5 pixels. But the sensor is outputing 4 
pixels/clk (See picture1 attached)

in my mind was doing something like in the picture2 attached.

But the problem is that with that solution I can't ouput data every 
clock after the pipeline delay... I need one solution to ouput data 
every clock without "deadtimes" in the output...

Any idea?

Thanks!

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Author: Schlumpf (Guest)
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You get the information with 20% less speed you actually need it. So how 
should this work "on the fly"?

E.g.
I give you every minute 4 apples and your task is, to pack 5 apples in a 
bag every minute.
That cannot work in an endless process.

If you know that there are 100 apples to pack you can store the incoming 
apples (4 every minute) in a container and start packing when there are 
20 apples in the contrainer.

So if you know that there are 10.000 pixels to process, store the first 
2.000 in a fifo-memory and then start processing.

Author: Mark Brandis (markbrandis)
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Schlumpf is right. Also, where is the fifth pixel in your table? I see 
only D1, D2, D3, D4. That looks like exactly four pixels to me.

Author: Jürgen S. (engineer)
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Do you want to use hard binning or soft binning?

Generally the way of data input reception has nothing to do with 
binning. You will have to buffer incoming pixels in an array of lines 
and post process partial fields in the conventional way. So 6 lines will 
be required to do this appropriately and join the quad words. In case of 
colour sensors, this can be combined with BAYER-processing. Basically 
you can do this with a conventional debayering 3x3->1 or with a extended 
5x5 and post processing for higher effort. In your case a 8x8 window 
might also be worth tinhking to handle possible aliasing effects when 
binning pixels of high resolution images. Care should be taken of the 
way of filtering.

Author: Enrique Perez (Guest)
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Hi the fith pixel is D1 of the next CLK. I need to add 5 pixels together 
and I am receiving only 4 pixels/clk. I need to do a hardware binning of 
the pixels like Jürgen Schuhmacher said in the post. But I thought that 
there was any posibility to add them on the fly without storing them in 
a any array.

Anyway I am wondering how can I estimate the minimum size of the buffer 
(FIFO) to output the binned pixels before storing the new incomming 
pixels?

Thanks a lot

Author: Schlumpf (Guest)
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Why do you want to store the binned pixel (outgoing) in a fifo?

Author: Jürgen S. (engineer)
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Enrique Perez wrote:
> I need to do a hardware binning of
> the pixels like Jürgen Schuhmacher said in the post.

With "hard" binning, I had the common method in mind, when physically 
adding the charges of the sensor pixel together by setting their outputs 
as a "wired or". This usually is triggered by setting the sensor to a 
specific mode and leads to a different timing.

In your case I assume you want to perform soft binning by reading each 
pixel's piece of information and adding them in the logic with an adder.

Although it is a hardware doing this, I call this "soft" because you do 
not really add the charges (a real process) but you do "only" add the 
abstract values of the intensity representing these charges (something 
logical).

Anyway you have to solve your timing issue and as far as I understand 
you description, you are getting all your pixels in sequence line by 
line, so you will have to create a block of 5 lines at least to get 
apply your 5x5 window to generate each of the filtered pixel. After this 
you apply a DDC by simply ignoring 4 out of 5 pixels and 4 out of lines. 
Basically you will use the pixel coordinates/numbers 2,7,12 in lines 
2,7,12 and so on to have a 2 dimensional binning.

Author: Jürgen S. (engineer)
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Ah! One question:

Do you have a 2D-Sensor or is it just a 1D-line-Sensor? This made clear 
why you want to add subsequent pixels of only one line. If this is the 
case, you need a simple register ram with only one input and one output 
where the output vector progresses with 5 steps as soon as enough pixels 
are available. Theoretically this is a FIFO but you might take my words 
regarding filtering into account. You should consider to use a FIFO, 
feed it with 4 words from left, read 5 words from right and push them 
into a 15 word register array. Then apply a filter over all these 
registers like shown in the upper part of the left image, with rising 
and falling behavior covering the adjacent pixels.

You can use also my "magic" triangular curve of weighted coefficients:
1,2,3,4,5,6,7,8,7,6,5,4,3,2,1 leading to a simply divider, namely 64.

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