Hello all. I'm new to VHDL programming so please forgive me in advance if i ask any bad question. I have an assignment to create a VHDL model and testbench for SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT device. I have started reading up as much as i can and time is running out. Could i get ideas, advice or any help on this topic? thanks
Naija Coding wrote: > I have an assignment to create a VHDL model and testbench for SINGLE > D-TYPE LATCH WITH 3-STATE OUTPUT device. Of course this is just a 10-minute job for a VHDL expert, but YOU got the excersise from your teacher. So, show what YOU have (at least you should have thought about it and written a few lines of code), then WE can discuss it. But no one here is intended to do your homework completely. > I have started reading up as much as i can and time is running out. You cannot learn by reading. You must learn by doing. Install one of the free toolchains (eg. from Altera, Lattice, Xilinx) on your PC and start working with it...
i have installed xilinx 14.1. Attached is what i have tried so far. Sorry it's my first time so still getting used to it. Any further help or advice? Am still working on it and my deadline is in 5 days
Naija Coding wrote: > Attached is what i have tried so far. Pls post the code again. Simply copy it this way into your post:
your VHDL code
Then everybody can copy and edit it... > Any further help or advice? Whats the problem with this code? Do you get error messages? Or is there strange behaviour in the simulation with your testbench (which you didn't post up to now)? > Any further help or advice? I'm missing LE in the code. and I would split up the whole thing in two steps with a internal signal: 1. depending on LE latch the input to a internal signal 2. depending on OE switch either this internal signal or 'Z' to the output You took 2 steps in 1 and began to stumble > Am still working on it and my deadline is in 5 days Then you must speed up a little bit. Your initial post was 4 days ago...