Hi. I designed the processor DorQ which is attached. It compiles fine in Quartus 2 but my business partners use Xilinx 8.1 & Xilinx 14.7 Version and on these software, it shows errors which are also attached to this thread. Could someone please provide a solution to this problem. Is there a setting we can change on Xilinx 8.1 & Xilinx 14.7 Version that will do away with the error messages. Thanks for your reply.
The message say, that there are two outputs are connected:
... ac923: acff port map (wire1(2500 downto 2500), wire1(2501 downto 2501), wire0(2501 downto 2501), wire0(2500 downto 2500)); bc1579: bcff port map (wire0(2501 downto 2501), wire0(2502 downto 2502), wire1(2502 downto 2502), wire1(2501 downto 2501)); ...
But your provided code is not human readable. Sorry, I can't help. Did the error also occur, if you try to generate a bitfile? Duke
Lewis Mbuthia wrote: > It compiles fine in Quartus 2 What target? You use extensively inout ports inside a FPGA. But FPGAs don't have bidirectional ports in them anymore. Thes also don't have a 'Z' inside. So every bidirectional connection must be resolved at compile time to a unidirectional mux-solution. That looks fairly tricky in the supplied code... Lewis Mbuthia wrote: > it shows errors which are also attached to this thread. Errors messages in PNG format? Why not as raw text as they are displayed in your computer? 1.png: the syntax check just tells, that theres no semicolon or comma missing. Nearly useless... 2.png: "Synthesize failed" is NOT a error message, its just a final result. Absolutely useless... 3.png: A multi-source means just: you connected two outputs together. Or in more sophisticated words: you have more than one driver on this signal. I don't see a solution for your problem. The design looks incredibly tricky. And it looks like it is not a design built for a FPGA.
: Edited by Moderator
WOW - That's what I call massive Crossposting. I thought, that the people nowadays know, not to crosspost? http://www.alteraforum.com/forum/showthread.php?t=46551 http://forums.xilinx.com/t5/New-Users-Forum/Xilinx-8-1-amp-Xilinx-14-7-Version-wiil-not-compile-my-design/td-p/535083 http://forums.xilinx.com/t5/General-Technical-Discussion/Xilinx-8-1-amp-Xilinx-14-7-Version-will-not-compile-my-design/td-p/536943 www.stackoverflow.com/questions/26563019/xilinx-8-1-xilinx-14-7-version- will-not-compile-my-design embdev.net/topic/347939 Only the entry in edaboard I'm missing? [edit: found it, but as another question. See below.] And what the hack is DorQ??? I can find only these interesting articles with naming such thing. Definitly worth the reading! Regarding to the crossposting and the mail-address, I asume that this is also from you, Lewis Mbuthia? http://www.edaboard.co.uk/partnership-request-t527308.html http://www.fpgarelated.com/comp.arch.fpga/thread/110054/partnership-request.php The code looks like a prank to me. But definitly not as a accelerating USB-Coprocessor. No explanation, what it is supposed to do. Whether it's complete. Nor the explanation of existing and running configurations... (I asume, there is no running configuration on a FPGA, and if there is, it isn't doing, what the descriptions says.) But it's also funny, to look further. Only one example of the company-page scientechworld.com/careers.php : "At Scientech we have a vision of where we want to go, and it's really exciting. [...]" :-) Thanks for the funny workbreak! Btw, it is often worth, to read the entries of embdev.net. ;-) (I'm impressed about your patiance, Lothar, to answer many of those questions! Good Job!) - ElKo