Using the Xilinx ISE Design Suite 14.7 version

Juan Guest #3844574
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I am using a Xilinx Spartan 3E-100 Basys2 module in order to make a 
design corresponding to a dynamic display circuit into the ISE design 
suite program (14.7 version), however when generating the program file, 
when I start to make a synthesis of the main program and its modules it 
returns me two errors and It says that one of them corresponds to the 
part of implementation of design, and the other to the translation of 
the program. If someone could help me find out why this happens or what 
would be the typical reasons why such errors occur, it would be really 
helpful.
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Juan Guest #3845949
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Forgive me for the response again, well about the error it actually 
says:

"#3/Dinamico/dinamico.ucf(22)]: NET "btn<3>" not found. Please verify 
that: 1. The specified design element actually exists in the original 
design. 2. The specified object is spelled correctly in the constraint 
source file".
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please Guest #3848181
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Juan,
Obviously you're lacking fundamental knowledge of FPGA development. You 
should find Demo-Projects for your Xilinx Spartan 3E-100 Basys2 module 
and use these to learn what's going on in .ucf files, during Synthesize, 
Translate, Map, Place&Route,...
Your (current) error is, that your .ucf file tries to constrain a signal 
called btn<3> (probably to a PIN location or maybe a timing net). But 
such a signal (wire) does not occur in your code (i.e. input/output 
list)
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