i have a question for whoever has the time.
I am writing a vhdl module to interface an IC through SPI.
The main functionality of the module is a FSM, using a few counters and
looping whenever is needed.
The IC to interface, requires a lot of writing to registers for
configuration, and then some writing and reading for normal operation,
all through SPI.
For example, i need to configure 30 something internal IC registers, to
get the IC ready for operation. So my FSM will loop 30 something times,
while incrementing a counter to keep track.
I am using a combinational proccess, where the counter above, selects
the correct SPI instruction, address and data to either read or write.
I am wondering if there is a better way for selecting SPI instruction,
address and data, because the combinational process becomes very quickly
Thank you in advance
SparkyT wrote:> I am wondering if there is a better way for selecting SPI instruction,> address and data, because the combinational process becomes very quickly> too long.
Use a RAM(ROM) and initialize it with the intitializing sequence...
Look at this LCD controller:
In it is a RAM which is used in double way: first it contains the
sequence to initialize the display, after initialisation it contains the
characters to be displayed...
> So my FSM will loop 30 something times, while incrementing a counter to> keep track.
You do not have to jump back to the very beginning of your "loop"...
SparkyT wrote:> I am writing a vhdl module to interface an IC through SPI.> The main functionality of the module is a FSM, using a few counters and> looping whenever is needed.
oops, what do you mean with 'looping'?
> The IC to interface, requires a lot of writing to registers for> configuration,
so, you have an SPI interface (most likely an SPI slave?) which receives
data via SPI, collects all bits together, and then presents you a e.g.
32bit register with a 'write-strobe' to your logic? If the cycletime of
the solution is too slow, you could easily pipeline this write operation
into your config-registers...
> and then some writing
same as above
> and reading for normal operation,> all through SPI.
now it gets interesting! Do you have a in-frame SPI protocoll or a
out-of-frame SPI protocoll? And what's the cycletime of the SPI, how is
the address to be read passed via SPI to your logic?
>> For example, i need to configure 30 something internal IC registers, to> get the IC ready for operation. So my FSM will loop 30 something times,> while incrementing a counter to keep track.
i simply have no idea what you are stating above... Without the .vhdl
files i can't even grasp what you are doing...
>> I am using a combinational proccess, where the counter above, selects> the correct SPI instruction, address and data to either read or write.>> I am wondering if there is a better way for selecting SPI instruction,> address and data, because the combinational process becomes very quickly> too long.
without having a clear description what you want to do (not based on
your non-working solution, just the problem!) and the requirements in
case of timing, latency, ... i think no one can give you an idea...
Lothar already mentioned embedded RAMs for data storage. Is this an
option for you? At least for some of the registers?
very interesting points, and i agree my description is not the best.
The FPGA will be the SPI master, and the IC is the SPI slave.
Let me just say that speed is not critical, i am way over some limits.
I just want to make my code simpler and more readable.
About looping, my fsm has about 30-35 states (so far). The first 5 are
the config loop, where each loop iteration configures a single register
on the SPI slave. After 30 times (configuring 29 registers, and
inquiring the state of the slave) i enter on the 6th state where i am in
the combinational process is already too long, and i haven't even
started enquiring the slave in normal operation.
I will also look into ROM (the fpga has embedded), as i need data to be
there even after power-down.
here is the begining on the combinational process.
obviously the "config_count" is the counter incremented by the fsm, to
give appropriate data to the SPI link.
SparkyT wrote:> About looping, my fsm has about 30-35 states (so far).
This is the ideal use for a RAM. Make config_count as an integer and
use it as the adress to read the addr_byte and data_byte from the
RAM in a way like that:
i was wondering how to adjust the SPI-master to a variable length SPI
tranfer. I need to interface an IC where i have SPI instructions that
are 1 byte long, 3 bytes long and 4 bytes long. The IC will always reply
on the third byte of the SPI variable transfer.
I have managed to change (well, trying) the example above, but keeping
the exact same logic. (repeating the sequence of the states, but
spi_bitcounter is not a generic. Its set every time according to need)
I have one Receive shift register (8bits), that registers MISO, and my
FSM knows when its the third byte, to read.
I have 3 Transmit shift registers used as follows,
-- 'tx_reg1' is 8 bits, used for 1 Byte SPI TRANSFER
-- 'tx_reg3' is 24 bits, used for 3 Bytes SPI TRANSFER
-- 'tx_reg4' is 32 bits, used for 4 Bytes SPI TRANSFER
The FSM knows what SPI length is needed for communication, and uses the
So far, so good. Simulations look ok, waiting for the hardware to start
testing. But the FSM has 49 states. I can already see some redudant
ones, that i will try to remove.
I guess the SPI-master example is your work. Very nice VHDL coding. So,
my question is how would you go about changing it to a variable length?
SparkyT wrote:> What about this?
Seems far to difficult. There is no need to have one 8 bit, one 16 bit
and one 32 bit SPI. I would configure only one SPI engine as an 32 bit
SPI (as you did). In that 32 bit register I would place the shorter 8
and 16 bit words to the correct place and then start a transmission with
the length of the bitcounter.
Michael Fischer did this already. You can find his adaption at the
bottom of the page: http://www.emb4fun.de/fpga/components/index.html