Hi every one
my working is to implement a circuit in FPGA ,i get the admittance
matric of circuit that be multiply it into current vector(value of
current vector changing with control signal state)
when the clock rise(posedge), elements of inverse admittance matric
(G11,G12,G21,G22) multiply into vector of current and when the clock
down(negedge), the vector of current be updated.
the code has been written in verilog.
the problems that ISE gives is that:
Line 29: r1 is not a constant
Line 30: y11 is not a constant
Line 31: y22 is not a constant
Line 21: Module <scircuit> ignored due to previous errors.
Mohammad Mothermohammad wrote:> i1 <=(vdc/r1)+j1;> Line 29: r1 is not a constant
ISE (and I belive other synthesis tools too) support only division by
You can change your divisior to fullfill this constrain or use IP core
for division or write your own code/FSM for division.
i change my code i want to define this parameter ,as input .
when program be run the values(G11,G12,G21,G22) get take from memory
the problem is how write code to access elements from memory
the new code is:
Mohammad Mothermohammad wrote:> the problem is how write code to access elements from memory
Take a look in the synthesis guide of your tool.
For Xilinx you can use the XST user guide (UG627). There you can find
a lot of (working) coding examples.