multiplier a matrice

Mohammad M. (mohammadmother) OP 2014-10-25 08:35 #3855810

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Hi every one
my working is to implement a circuit in FPGA ,i get the admittance 
matric of circuit that be multiply it into current vector(value of 
current vector changing with control signal state)
when the clock rise(posedge), elements of inverse admittance matric 
(G11,G12,G21,G22) multiply into vector of current and when the clock 
down(negedge), the vector of current be updated.
the code has been written in verilog.
the problems that ISE gives is that:

Line 29: r1 is not a constant
Line 30: y11 is not a constant
Line 31: y22 is not a constant
Line 21: Module <scircuit> ignored due to previous errors.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// Create Date:    17:21:30 10/24/2014 
// Design Name: 
// Module Name:    scircuit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
// Dependencies: 
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//////////////////////////////////////////////////////////////////////////////////
module scircuit(
    input control,
    input clk,
    input reset,
    output reg [15:0] v1,v2
reg  [15:0] r1=1'b1, G1=1'b1 , R=4'b1010, vdc=8'b100100;
reg signed [15:0] y11=(1/r1)+G1 ,y12=-G1 ,y21=-G1 ,y22=R+G1;
reg signed [15:0] yy=(1/((y11*y22)-(y12*y21)));
reg signed [15:0] G11=(y22/yy) ,G12=(-y12/yy) ,G21=(-y21/yy) ,G22=(y11/yy);
reg signed [15:0] j1=0000000000000000;
reg signed [15:0] j2=0000000000000000;
reg signed [15:0] v11,v22,i1,i2;
always @(posedge clk)
  if (reset == 1)
       begin     
       end  //end if(reset ==1)
       begin
        i1 <=(vdc/r1)+j1;
        i2 <= -j1;
        v11 <= (G11*i1) + (G12*i2) ;
        v22 <= (G21*i2) + (G22*i2) ;
      v1 <= v11;
      v2 <= v22;
      end
      always @(negedge clk)
          case(control)
            j1 <=-G1*(v1-v2);
               j1 <= G1*(v1-v2);
   endcase
endmodule

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Duke Scarring Guest 2014-10-27 08:05 #3858030

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Mohammad Mothermohammad wrote:
> i1 <=(vdc/r1)+j1;
> Line 29: r1 is not a constant

ISE (and I belive other synthesis tools too) support only division by 
2**n.

You can change your divisior to fullfill this constrain or use IP core 
for division or write your own code/FSM for division.

Duke

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Mohammad M. (mohammadmother) OP 2014-10-27 13:46 #3858504

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thanks Duke
i change my code i want to define this parameter ,as input .
when program be run the values(G11,G12,G21,G22) get take from memory
the problem is how write code to access elements from memory
 the new code is:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// Create Date:    17:21:30 10/24/2014 
// Design Name: 
// Module Name:    scircuit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
// Dependencies: 
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//////////////////////////////////////////////////////////////////////////////////
module scircuit(
    input control,
    input clk,
    input reset,
    input G11,G12,G21,G22;
    output reg [15:0] v1,v2
reg signed [15:0]  j1,j2;
reg signed [15:0] v11,v22,i1,i2;
always @(posedge clk)
  if (reset == 1)
       begin     
     end  //end if(reset ==1)
       begin
        i1 <=(vdc/r1)+j1;
        i2 <= -j1;
        v11 <= (G11*i1) + (G12*i2) ;
        v22 <= (G21*i2) + (G22*i2) ;
      v1 <= v11;
      v2 <= v22;
      end
      always @(negedge clk)
          case(control)
            j1 <=-G1*(v11-v22);
              j1 <= G1*(v11-v22);
   endcase
endmodule

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Duke Scarring Guest 2014-10-27 14:43 #3858578

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Mohammad Mothermohammad wrote:
> the problem is how write code to access elements from memory
Take a look in the synthesis guide of your tool.

For Xilinx you can use the XST user guide (UG627). There you can find 
a lot of (working) coding examples.

Duke

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