Forum: FPGA, VHDL & Verilog mux using system generator

von REKHA V. (Company: college of engineering chengan) (rekhavp)

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I want to create a cascaded mux stage using system generator. how is it 

von antony mathew (Guest)

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U can use an Hdl to code it. Vhdl or verilog. Use case or if else .

von lkmiller (Guest)

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REKHA V P wrote:
> using system generator
Which one?


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