Hi all Perhaps someone with Lattice experience can answer this for me. I am building a design on a MachXO2 using the EFB for I2C MASTER communication I builtmy own state machine for writing and reading to the wishbone bus. I have success in Reading and Writing EFB registers VIA WISHBONE and have properly written all registers like TXDR, Command Register, Control Register of Secondary i2c . But in simulation i dont see any kind of activity in SCL and SDA lines from EFB primitive block... Both lines are always in High Impedence (Blue in Modelsim, Green if Aldec Simulator Used). In Test Bench i do 1. An initial Reset 2. Enable I2c core by writing 0x80 to 0x4a register(Control) 3. Write Clock Prescale Registers 0x4c and 0x4d with proper value 4. Read back and verified these registers 5. Wrote Data 0xF1to TXDR register 6. Issued 0x94 to Command Register for a (Start + Write) But i dont see any activity in SCL , SDA liness.... Am i missing something here.. Any help would be very helpful... Thanks.... Device : MACHXO2-7000 Tool : Lattice Diamond 3.1.0.96 (64 bit)
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#3841016
In case you are using verilog, try to add to your testbench toplevel.
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This simulates the pullup resistors.
thank you for the reply... i am using vhdl for RTL.. will try to mimic pull up in testbench as u suggested. But my another doubt is that even if we dont use this pull up , we should be able to see the activity of SCL and SDA as between 'Z' and '0'. Please correct me if i am wrong in this concept...
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#3841570
Antony Mathew wrote: > Am i missing something here.. Any help would be very helpful... > Thanks.... Is your code top secret, or can you share your code? In the latter case I can give it a try on my simulator... Duke
Duke Scarring wrote: > Antony Mathew wrote: >> Am i missing something here.. Any help would be very helpful... >> Thanks.... > Is your code top secret, or can you share your code? > In the latter case I can give it a try on my simulator... > > Duke Ok duke .. thank you for the effort please see the attached .zip containing project /rtl contains the user logic wishbone master and a top module to contain the efb block and user wishbone master /tb contains the test bench which initiates the read/write using user wishbone master /syn contains the lattice diamond project /ipcore contains the efb i2c ipexpress generated files /sim contains a 'wishbone.do' which can be used for simulation if u are using modelsim
Lattice User wrote: > In case you are using verilog, try to add to your testbench toplevel. > >
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> > This simulates the pullup resistors. Hi Lattice User I tried as u told... now Issue is solved i guess... Below lines added to VHDL testbench
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Now i can see SDA, SCL lines toggling properly as per data in TXDR register Thank you all for the support....