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Forum: FPGA, VHDL & Verilog accurate counter


von Mohammad M. (mohammadmother)


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hi every body
i write a vhdl code that is nearly accurate counter
every 1.34 s the LED will be ++
(2^27*10ns = 1.34 s )
please tell me what is it's problem because in ISIM i don't got the 
answer
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----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    08:48:18 09/28/2014 
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-- Design Name: 
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-- Module Name:    count - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.STD_logic_unsigned.ALL;
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity count is
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    Port ( clk : in  STD_LOGIC;
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           reset : in  STD_LOGIC;
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           sw1 : in  STD_LOGIC;
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           LED : out std_logic_vector(7 downto 0)); 
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end count;
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architecture Behavioral of count is
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begin
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process (clk,reset,sw1)
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variable c :std_logic_vector(7 downto 0):="00000000";
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variable counter :std_logic_vector(27 downto 0):="0000000000000000000000000000";
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begin
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   if reset='1' then
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        LED <= "00000000";
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     elsif sw1='1' then
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         LED <= "11111111";
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     elsif(clk'event and clk='1') then
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       counter := counter +1 ;
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          if (counter ="1000000000000000000000000000") then
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                c:=c+1;      
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                LED<=c;
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             counter:="0000000000000000000000000000";
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        end if;
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    end if;
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end process;    
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end Behavioral;

: Edited by Moderator
von asd (Guest)


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just some tipps:

- no need to use variables here, use signals instead for the counting 
logic. (and read about the difference of signals and variables)

- it's better style to use IEEE.NUMERIC_STD.ALL to calculate in vhdl and 
don't calculate with logic_vectors directly, but instead with integer or 
natural

- you can use hex-format for more compact style: x"00" for "00000000"

von Lothar M. (lkmiller) (Moderator)


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First: please use the vhdl tags areund your VHDL code:
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[vhdl]VHDL code[/vhdl]

Then this:
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variable counter :std_logic_vector(27 downto 0):="0000000000000000000000000000";
Why do you use a variable?
Why don't you use an integer?

And where did you find this:
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   if reset='1' then
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      LED <= "00000000";
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   elsif sw1='1' then
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      LED <= "11111111";
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   elsif(clk'event and clk='1') then
An asynchronous reset AND additionally a conbinatorial reset. Thats 
plain rubbish!

This here:
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counter:="0000000000000000000000000000";
Could be shortened to that:
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counter:=(others=>'0');


Mohammad Mothermohammad wrote:
> i write a vhdl code that is nearly accurate
My VHDL code usually is exactly accurate. Whats the problem with 
yours?

> please tell me what is it's problem because in ISIM i don't got the answer
What error messages do you get? What do you expect and what happens 
instead?

I would do it like this:
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library IEEE; 
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use IEEE.STD_LOGIC_1164.ALL; 
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use IEEE.NUMERIC_STD.ALL; 
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entity BlinkLED is 
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    Port ( clk : in  STD_LOGIC; 
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           led : out  STD_LOGIC); 
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end BlinkLED; 
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architecture Behavioral of BlinkLED is 
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                                                    -- let the synthesizer do the hard work!
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signal c : integer range 0 to 1340000000/10-1 := 0; -- 1.34s at 100MHz = 1340000000ns/10ns
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signal x : std_logic:= '0';
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begin 
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   process begin  
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      wait until rising_edge(clk); -- wait till next clock
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      if (c<1340000000/10-1) then  -- check the counter
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          c <= c+1;                -- if less: count up
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      else                         -- if reached:
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          c <= 0;                  -- reset counter
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          x <= not x;              -- and toggle the local signal x
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      end if; 
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   end process; 
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   led <= x;                       -- hand x over to the LED
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end Behavioral;

: Edited by Moderator
von Mohammad M. (mohammadmother)


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thank you for every one i modified the code and implement this into FPGA 
and it's work.

correct code is:
1
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    08:48:18 09/28/2014 
6
-- Design Name: 
7
-- Module Name:    count - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
----------------------------------------------------------------------------------
20
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.STD_logic_unsigned.ALL;
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity count is
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    Port ( clk : in  STD_LOGIC;
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           reset : in  STD_LOGIC;
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           sw1 : in  STD_LOGIC;
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           LED : out std_logic_vector(7 downto 0)); 
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end count;
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architecture Behavioral of count is
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begin
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process (clk,reset,sw1)
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variable c :std_logic_vector(7 downto 0):="00000000";
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variable counter :std_logic_vector(26 downto 0):="000000000000000000000000000";
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begin
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if(clk'event and clk='1') then
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      if reset='1' then
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         LED <= "00000000";
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          counter := "000000000000000000000000000";
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       c:="00000000";   
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     elsif sw1='1' then
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         LED <= "11111111";
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          c := "11111111";
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       LED <=c;  
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      -- for i in 0 to 10000000 loop
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           --      if (i=10000000) then
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         --      counter:="000000000000000000000000000";
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             --    c:="00000000";
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              --  LED <= c;
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             --end if;
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              --  end loop  ;
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         else
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        counter := counter +1 ;
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           if (counter ="101111101011110000100000000") then
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                c:=c+1;      
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                LED<=c;
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              counter:="000000000000000000000000000";
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            end if;
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     end if;
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end if;
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end process;    
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end Behavioral;

: Edited by User

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