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Forum: FPGA, VHDL & Verilog accurate counter

von Mohammad M. (mohammadmother)

2014-09-28 16:44

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hi every body
i write a vhdl code that is nearly accurate counter
every 1.34 s the LED will be ++
(2^27*10ns = 1.34 s )
please tell me what is it's problem because in ISIM i don't got the 
answer

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- Create Date:    08:48:18 09/28/2014 
-- Design Name: 
-- Module Name:    count - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- Dependencies: 
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.STD_logic_unsigned.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
           LED : out std_logic_vector(7 downto 0)); 
end count;
architecture Behavioral of count is
process (clk,reset,sw1)
variable c :std_logic_vector(7 downto 0):="00000000";
variable counter :std_logic_vector(27 downto 0):="0000000000000000000000000000";
   if reset='1' then
        LED <= "00000000";
     elsif sw1='1' then
         LED <= "11111111";
     elsif(clk'event and clk='1') then
       counter := counter +1 ;
          if (counter ="1000000000000000000000000000") then
                LED<=c;
             counter:="0000000000000000000000000000";
        end if;
    end if;
end process;    
end Behavioral;

2014-09-29 08:20: Edited by Moderator

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Re: accurate counter

von asd (Guest)

2014-09-29 08:41

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just some tipps:

- no need to use variables here, use signals instead for the counting 
logic. (and read about the difference of signals and variables)

- it's better style to use IEEE.NUMERIC_STD.ALL to calculate in vhdl and 
don't calculate with logic_vectors directly, but instead with integer or 
natural

- you can use hex-format for more compact style: x"00" for "00000000"

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Re: accurate counter

von Lothar M. (lkmiller) (Moderator)

2014-09-29 09:37

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First: please use the vhdl tags areund your VHDL code:

1	[vhdl]VHDL code[/vhdl]


Then this:

variable counter :std_logic_vector(27 downto 0):="0000000000000000000000000000";

Why do you use a variable?
Why don't you use an integer?

And where did you find this:

   if reset='1' then
      LED <= "00000000";
   elsif sw1='1' then
      LED <= "11111111";
   elsif(clk'event and clk='1') then

An asynchronous reset AND additionally a conbinatorial reset. Thats 
plain rubbish!

This here:

counter:="0000000000000000000000000000";

Could be shortened to that:

counter:=(others=>'0');



Mohammad Mothermohammad wrote:
> i write a vhdl code that is nearly accurate
My VHDL code usually is exactly accurate. Whats the problem with 
yours?

> please tell me what is it's problem because in ISIM i don't got the answer
What error messages do you get? What do you expect and what happens 
instead?

I would do it like this:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL; 
entity BlinkLED is 
    Port ( clk : in  STD_LOGIC; 
           led : out  STD_LOGIC); 
end BlinkLED; 
architecture Behavioral of BlinkLED is 
                                                    -- let the synthesizer do the hard work!
signal c : integer range 0 to 1340000000/10-1 := 0; -- 1.34s at 100MHz = 1340000000ns/10ns
signal x : std_logic:= '0';
   process begin  
      wait until rising_edge(clk); -- wait till next clock
      if (c<1340000000/10-1) then  -- check the counter
          c <= c+1;                -- if less: count up
      else                         -- if reached:
          c <= 0;                  -- reset counter
          x <= not x;              -- and toggle the local signal x
      end if; 
   end process; 
   led <= x;                       -- hand x over to the LED
end Behavioral;

2014-09-29 09:43: Edited by Moderator

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Re: accurate counter

von Mohammad M. (mohammadmother)

2014-10-25 08:40

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thank you for every one i modified the code and implement this into FPGA 
and it's work.

correct code is:

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- Create Date:    08:48:18 09/28/2014 
-- Design Name: 
-- Module Name:    count - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- Dependencies: 
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.STD_logic_unsigned.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
           LED : out std_logic_vector(7 downto 0)); 
end count;
architecture Behavioral of count is
process (clk,reset,sw1)
variable c :std_logic_vector(7 downto 0):="00000000";
variable counter :std_logic_vector(26 downto 0):="000000000000000000000000000";
if(clk'event and clk='1') then
      if reset='1' then
         LED <= "00000000";
          counter := "000000000000000000000000000";
       c:="00000000";   
     elsif sw1='1' then
         LED <= "11111111";
          c := "11111111";
       LED <=c;  
      -- for i in 0 to 10000000 loop
           --      if (i=10000000) then
         --      counter:="000000000000000000000000000";
             --    c:="00000000";
              --  LED <= c;
             --end if;
              --  end loop  ;
         else
        counter := counter +1 ;
           if (counter ="101111101011110000100000000") then
                LED<=c;
              counter:="000000000000000000000000000";
            end if;
     end if;
end process;    
end Behavioral;

2014-10-25 08:41: Edited by User

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