Guest
#3879948
Hello,
I want to create a circuit which has two inputs a clock and an enable
and three outputs. What I want this circuit to do is that it has a
variable (cont) that goes from "00" to "11" and two of the outputs
(sal_1 and sal_2) take the values of cont(0) and cont(1) and go to the
inputs of a ttl ic (AND , OR, XOR) and then the output of the ttl ic
goes back to the circuit and is saved (results) after that, the vector
that is created from the differents results of the ttl ic ouputs is
compared with vectors already predefined and find the one that matches
it and returns the value.
I have a hard time with the output and then input times, it seems that
there is a special way to do this.
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ttl_finder is
port( clk, ena, sal_ttl : in std_logic;
sal_1, sal_2 : out std_logic;
sal_f : out std_logic_vector(3 downto 0));
end entity;
architecture ttl_tester of ttl_finder is
signal cont : std_logic_vector(1 downto 0) := "00";
signal results : std_logic_vector(3 downto 0) := "0000";
begin
process(clk, ena)
variable c : std_logic;
variable d : std_logic;
variable e : std_logic;
begin
if ena = '1' then
if cont < "11" then
sal_1 <= cont(0);
sal_2 <= cont(1);
if rising_edge(clk) then
results(conv_integer(cont)) <= sal_ttl;
end if;
cont <= cont + 1;
else
sal_1 <= cont(0);
sal_2 <= cont(1);
if rising_edge(clk) then
results(conv_integer(cont)) <= sal_ttl;
end if;
cont <= "00";
end if;
end if;
end process;
sal_f <= results;
end ttl_tester;