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Forum: FPGA, VHDL & Verilog DE0_NANO_ADC


DE0_NANO_ADC
von jeorges F. (Company: xlue) (khal1985)

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Hi everyone,

I have a DE0_NANO board, i try to use the ADC(ADC128S022) integrated in 
the board but i don't understand the sample code of the ADC module given 
by terasic.

the code is below :
1
module ADC_CTRL  (  

2
          iRST,

3
          iCLK,

4
          iCLK_n,

5
          iGO,

6
          iCH,

7
          oLED,

8
          

9
          oDIN,

10
          oCS_n,

11
          oSCLK,

12
          iDOUT

13
        );

14
          

15
input        iRST;

16
input        iCLK;

17
input        iCLK_n;

18
input        iGO;

19
input  [2:0]    iCH;

20
output  [7:0]    oLED;

21
22
output        oDIN;

23
output        oCS_n;

24
output        oSCLK;

25
input        iDOUT;

26
27
reg          data;

28
reg          go_en;

29
wire  [2:0]    ch_sel;

30
reg          sclk;

31
reg    [3:0]    cont;

32
reg    [3:0]    m_cont;

33
reg    [11:0]    adc_data;

34
reg    [7:0]    led;

35
36
assign  oCS_n    =  ~go_en;

37
assign  oSCLK    =  (go_en)? iCLK:1;

38
assign  oDIN    =  data;

39
assign  ch_sel    =  iCH;

40
assign  oLED    =  led;

41
42
always@(posedge iGO or negedge iRST)

43
begin

44
  if(!iRST)

45
    go_en  <=  0;

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  else

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  begin

48
    if(iGO)

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      go_en  <=  1;

50
  end

51
end

52
53
always@(posedge iCLK or negedge go_en)

54
begin

55
  if(!go_en)

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    cont  <=  0;

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  else

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  begin

59
    if(iCLK)

60
      cont  <=  cont + 1;

61
  end

62
end

63
64
always@(posedge iCLK_n)

65
begin

66
  if(iCLK_n)

67
    m_cont  <=  cont;

68
end

69
70
always@(posedge iCLK_n or negedge go_en)

71
begin

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  if(!go_en)

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    data  <=  0;

74
  else

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  begin

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    if(iCLK_n)

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    begin

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      if (cont == 2)

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        data  <=  iCH[2];

80
      else if (cont == 3)

81
        data  <=  iCH[1];

82
      else if (cont == 4)

83
        data  <=  iCH[0];

84
      else

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        data  <=  0;

86
    end

87
  end

88
end

89
90
always@(posedge iCLK or negedge go_en)

91
begin

92
  if(!go_en)

93
  begin

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    adc_data  <=  0;

95
    led      <=  8'h00;

96
  end

97
  else

98
  begin

99
    if(iCLK)

100
    begin

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      if (m_cont == 4)

102
        adc_data[11]  <=  iDOUT;

103
      else if (m_cont == 5)

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        adc_data[10]  <=  iDOUT;

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      else if (m_cont == 6)

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        adc_data[9]    <=  iDOUT;

107
      else if (m_cont == 7)

108
        adc_data[8]    <=  iDOUT;

109
      else if (m_cont == 8)

110
        adc_data[7]    <=  iDOUT;

111
      else if (m_cont == 9)

112
        adc_data[6]    <=  iDOUT;

113
      else if (m_cont == 10)

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        adc_data[5]    <=  iDOUT;

115
      else if (m_cont == 11)

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        adc_data[4]    <=  iDOUT;

117
      else if (m_cont == 12)

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        adc_data[3]    <=  iDOUT;

119
      else if (m_cont == 13)

120
        adc_data[2]    <=  iDOUT;

121
      else if (m_cont == 14)

122
        adc_data[1]    <=  iDOUT;

123
      else if (m_cont == 15)

124
        adc_data[0]    <=  iDOUT;

125
      else if (m_cont == 1)

126
        led  <=  adc_data[11:4];

127
    end

128
  end

129
end

130
131
endmodule


I don't understand why we use two clocks:iCLK,iCLK_n,
These clocks as generated as follows:
1
altpll_component.bandwidth_type = "AUTO",

2
    altpll_component.clk0_divide_by = 25,

3
    altpll_component.clk0_duty_cycle = 50,

4
    altpll_component.clk0_multiply_by = 1,

5
    altpll_component.clk0_phase_shift = "0",

6
    altpll_component.clk1_divide_by = 25,

7
    altpll_component.clk1_duty_cycle = 50,

8
    altpll_component.clk1_multiply_by = 1,

9
    altpll_component.clk1_phase_shift = "250000",

10
    altpll_component.compensate_clock = "CLK0",

11
    altpll_component.inclk0_input_frequency = 20000,

Can someone highlights me this issue please? it's possible to do it 
using one clock ?
Best regards

  


  




  

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    Re: DE0_NANO_ADC
  


  

    

      von
      
        Lothar M.
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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jeorges FrenchRivera wrote:
> assign  oSCLK    =  (go_en)? iCLK:1;
This gated clock is not a good design practice. If a clock has to be 
output to a FPGA pin, a DDR regigster should be used...

> but i don't understand the sample code of the ADC module given by
> terasic.
Did you try it? If so: what specific part do you not understand?

> These clocks as generated as follows:
I cannot find them there. The only entry of those signals is the port 
list of the ADC_CTRL module.

> it's possible to do it using one clock ?
Usually it the best way to use only one clock and only one edge of 
that clock. Using the other edge of that clock also means a physically 
doubling of the clock frequency. But here it is senseless, because a PLL 
is used and this could be easily configured to deliver the double 
clock...

  


  




  

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        jeorges FrenchRivera (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Thank you Miler for you reply.

>I cannot find them there. The only entry of those signals is the port
>list of the ADC_CTRL module.
You are right i forget to precise that the clocks generation is given in 
another file
1
//=======================================================

2
//  REG/WIRE declarations

3
//=======================================================

4
wire            wSPI_CLK;

5
wire            wSPI_CLK_n;

6
7
//=======================================================

8
//  Structural coding

9
//=======================================================

10
SPIPLL    U0  (

11
            .inclk0(CLOCK_50),

12
            .c0(wSPI_CLK),

13
            .c1(wSPI_CLK_n)

14
          );

15
16
ADC_CTRL    U1  (

17
            .iRST(KEY[0]),

18
            .iCLK(wSPI_CLK),

19
            .iCLK_n(wSPI_CLK_n),

20
            .iGO(KEY[1]),

21
            .iCH(SW[2:0]),

22
            .oLED(LED),

23
            

24
            .oDIN(ADC_SADDR),

25
            .oCS_n(ADC_CS_N),

26
            .oSCLK(ADC_SCLK),

27
            .iDOUT(ADC_SDAT)

28
          );

29
30
31
endmodule


>Did you try it? If so: what specific part do you not understand?
Yes i tried it and it works but when i compare with the datasheet of 
ADC, i didn't understand cont and m_cont values and the aims to use two 
Clocks.
I hope that it's clear for you.

Best regards

  


  




  

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    Re: DE0_NANO_ADC
  


  

    

      von
      
        Lothar M.
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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jeorges FrenchRivera wrote:
> and the aims to use two Clocks.
"Ease" of design? Or stupidity? Who knows...

As I said the design could be easily made with only one clock with the 
doubled frequency. Then there would aslo be no need for the gated SCLK.

  


  




  

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        jeorges FrenchRivera (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Ok thanks

  


  




  

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