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Forum: FPGA, VHDL & Verilog DE0_NANO_ADC


von jeorges F. (Company: xlue) (khal1985)


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Hi everyone,

I have a DE0_NANO board, i try to use the ADC(ADC128S022) integrated in 
the board but i don't understand the sample code of the ADC module given 
by terasic.

the code is below :
module ADC_CTRL  (  
          iRST,
          iCLK,
          iCLK_n,
          iGO,
          iCH,
          oLED,
          
          oDIN,
          oCS_n,
          oSCLK,
          iDOUT
        );
          
input        iRST;
input        iCLK;
input        iCLK_n;
input        iGO;
input  [2:0]    iCH;
output  [7:0]    oLED;

output        oDIN;
output        oCS_n;
output        oSCLK;
input        iDOUT;

reg          data;
reg          go_en;
wire  [2:0]    ch_sel;
reg          sclk;
reg    [3:0]    cont;
reg    [3:0]    m_cont;
reg    [11:0]    adc_data;
reg    [7:0]    led;

assign  oCS_n    =  ~go_en;
assign  oSCLK    =  (go_en)? iCLK:1;
assign  oDIN    =  data;
assign  ch_sel    =  iCH;
assign  oLED    =  led;

always@(posedge iGO or negedge iRST)
begin
  if(!iRST)
    go_en  <=  0;
  else
  begin
    if(iGO)
      go_en  <=  1;
  end
end

always@(posedge iCLK or negedge go_en)
begin
  if(!go_en)
    cont  <=  0;
  else
  begin
    if(iCLK)
      cont  <=  cont + 1;
  end
end

always@(posedge iCLK_n)
begin
  if(iCLK_n)
    m_cont  <=  cont;
end

always@(posedge iCLK_n or negedge go_en)
begin
  if(!go_en)
    data  <=  0;
  else
  begin
    if(iCLK_n)
    begin
      if (cont == 2)
        data  <=  iCH[2];
      else if (cont == 3)
        data  <=  iCH[1];
      else if (cont == 4)
        data  <=  iCH[0];
      else
        data  <=  0;
    end
  end
end

always@(posedge iCLK or negedge go_en)
begin
  if(!go_en)
  begin
    adc_data  <=  0;
    led      <=  8'h00;
  end
  else
  begin
    if(iCLK)
    begin
      if (m_cont == 4)
        adc_data[11]  <=  iDOUT;
      else if (m_cont == 5)
        adc_data[10]  <=  iDOUT;
      else if (m_cont == 6)
        adc_data[9]    <=  iDOUT;
      else if (m_cont == 7)
        adc_data[8]    <=  iDOUT;
      else if (m_cont == 8)
        adc_data[7]    <=  iDOUT;
      else if (m_cont == 9)
        adc_data[6]    <=  iDOUT;
      else if (m_cont == 10)
        adc_data[5]    <=  iDOUT;
      else if (m_cont == 11)
        adc_data[4]    <=  iDOUT;
      else if (m_cont == 12)
        adc_data[3]    <=  iDOUT;
      else if (m_cont == 13)
        adc_data[2]    <=  iDOUT;
      else if (m_cont == 14)
        adc_data[1]    <=  iDOUT;
      else if (m_cont == 15)
        adc_data[0]    <=  iDOUT;
      else if (m_cont == 1)
        led  <=  adc_data[11:4];
    end
  end
end

endmodule

I don't understand why we use two clocks:iCLK,iCLK_n,
These clocks as generated as follows:
altpll_component.bandwidth_type = "AUTO",
    altpll_component.clk0_divide_by = 25,
    altpll_component.clk0_duty_cycle = 50,
    altpll_component.clk0_multiply_by = 1,
    altpll_component.clk0_phase_shift = "0",
    altpll_component.clk1_divide_by = 25,
    altpll_component.clk1_duty_cycle = 50,
    altpll_component.clk1_multiply_by = 1,
    altpll_component.clk1_phase_shift = "250000",
    altpll_component.compensate_clock = "CLK0",
    altpll_component.inclk0_input_frequency = 20000,
Can someone highlights me this issue please? it's possible to do it 
using one clock ?
Best regards

von Lothar M. (lkmiller) (Moderator)


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jeorges FrenchRivera wrote:
> assign  oSCLK    =  (go_en)? iCLK:1;
This gated clock is not a good design practice. If a clock has to be 
output to a FPGA pin, a DDR regigster should be used...

> but i don't understand the sample code of the ADC module given by
> terasic.
Did you try it? If so: what specific part do you not understand?

> These clocks as generated as follows:
I cannot find them there. The only entry of those signals is the port 
list of the ADC_CTRL module.

> it's possible to do it using one clock ?
Usually it the best way to use only one clock and only one edge of 
that clock. Using the other edge of that clock also means a physically 
doubling of the clock frequency. But here it is senseless, because a PLL 
is used and this could be easily configured to deliver the double 
clock...

von jeorges FrenchRivera (Guest)


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Thank you Miler for you reply.

>I cannot find them there. The only entry of those signals is the port
>list of the ADC_CTRL module.
You are right i forget to precise that the clocks generation is given in 
another file
//=======================================================
//  REG/WIRE declarations
//=======================================================
wire            wSPI_CLK;
wire            wSPI_CLK_n;

//=======================================================
//  Structural coding
//=======================================================
SPIPLL    U0  (
            .inclk0(CLOCK_50),
            .c0(wSPI_CLK),
            .c1(wSPI_CLK_n)
          );

ADC_CTRL    U1  (
            .iRST(KEY[0]),
            .iCLK(wSPI_CLK),
            .iCLK_n(wSPI_CLK_n),
            .iGO(KEY[1]),
            .iCH(SW[2:0]),
            .oLED(LED),
            
            .oDIN(ADC_SADDR),
            .oCS_n(ADC_CS_N),
            .oSCLK(ADC_SCLK),
            .iDOUT(ADC_SDAT)
          );


endmodule

>Did you try it? If so: what specific part do you not understand?
Yes i tried it and it works but when i compare with the datasheet of 
ADC, i didn't understand cont and m_cont values and the aims to use two 
Clocks.
I hope that it's clear for you.

Best regards

von Lothar M. (lkmiller) (Moderator)


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jeorges FrenchRivera wrote:
> and the aims to use two Clocks.
"Ease" of design? Or stupidity? Who knows...

As I said the design could be easily made with only one clock with the 
doubled frequency. Then there would aslo be no need for the gated SCLK.

von jeorges FrenchRivera (Guest)


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Ok thanks

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