DE0_NANO_ADC

jeorges F. OP (Company: xlue) #3881323
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Hi everyone,

I have a DE0_NANO board, i try to use the ADC(ADC128S022) integrated in 
the board but i don't understand the sample code of the ADC module given 
by terasic.

the code is below :
1
module ADC_CTRL  (  

2
          iRST,

3
          iCLK,

4
          iCLK_n,

5
          iGO,

6
          iCH,

7
          oLED,

8
          

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          oDIN,

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          oCS_n,

11
          oSCLK,

12
          iDOUT

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        );

14
          

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input        iRST;

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input        iCLK;

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input        iCLK_n;

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input        iGO;

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input  [2:0]    iCH;

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output  [7:0]    oLED;

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output        oDIN;

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output        oCS_n;

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output        oSCLK;

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input        iDOUT;

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reg          data;

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reg          go_en;

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wire  [2:0]    ch_sel;

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reg          sclk;

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reg    [3:0]    cont;

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reg    [3:0]    m_cont;

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reg    [11:0]    adc_data;

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reg    [7:0]    led;

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assign  oCS_n    =  ~go_en;

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assign  oSCLK    =  (go_en)? iCLK:1;

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assign  oDIN    =  data;

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assign  ch_sel    =  iCH;

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assign  oLED    =  led;

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always@(posedge iGO or negedge iRST)

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begin

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  if(!iRST)

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    go_en  <=  0;

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  else

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  begin

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    if(iGO)

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      go_en  <=  1;

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  end

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end

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always@(posedge iCLK or negedge go_en)

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begin

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  if(!go_en)

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    cont  <=  0;

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  else

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  begin

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    if(iCLK)

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      cont  <=  cont + 1;

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  end

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end

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always@(posedge iCLK_n)

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begin

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  if(iCLK_n)

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    m_cont  <=  cont;

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end

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always@(posedge iCLK_n or negedge go_en)

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begin

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  if(!go_en)

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    data  <=  0;

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  else

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  begin

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    if(iCLK_n)

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    begin

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      if (cont == 2)

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        data  <=  iCH[2];

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      else if (cont == 3)

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        data  <=  iCH[1];

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      else if (cont == 4)

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        data  <=  iCH[0];

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      else

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        data  <=  0;

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    end

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  end

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end

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always@(posedge iCLK or negedge go_en)

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begin

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  if(!go_en)

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  begin

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    adc_data  <=  0;

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    led      <=  8'h00;

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  end

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  else

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  begin

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    if(iCLK)

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    begin

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      if (m_cont == 4)

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        adc_data[11]  <=  iDOUT;

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      else if (m_cont == 5)

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        adc_data[10]  <=  iDOUT;

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      else if (m_cont == 6)

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        adc_data[9]    <=  iDOUT;

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      else if (m_cont == 7)

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        adc_data[8]    <=  iDOUT;

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      else if (m_cont == 8)

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        adc_data[7]    <=  iDOUT;

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      else if (m_cont == 9)

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        adc_data[6]    <=  iDOUT;

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      else if (m_cont == 10)

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        adc_data[5]    <=  iDOUT;

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      else if (m_cont == 11)

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        adc_data[4]    <=  iDOUT;

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      else if (m_cont == 12)

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        adc_data[3]    <=  iDOUT;

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      else if (m_cont == 13)

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        adc_data[2]    <=  iDOUT;

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      else if (m_cont == 14)

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        adc_data[1]    <=  iDOUT;

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      else if (m_cont == 15)

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        adc_data[0]    <=  iDOUT;

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      else if (m_cont == 1)

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        led  <=  adc_data[11:4];

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    end

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  end

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end

130


131
endmodule


I don't understand why we use two clocks:iCLK,iCLK_n,
These clocks as generated as follows:
1
altpll_component.bandwidth_type = "AUTO",

2
    altpll_component.clk0_divide_by = 25,

3
    altpll_component.clk0_duty_cycle = 50,

4
    altpll_component.clk0_multiply_by = 1,

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    altpll_component.clk0_phase_shift = "0",

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    altpll_component.clk1_divide_by = 25,

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    altpll_component.clk1_duty_cycle = 50,

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    altpll_component.clk1_multiply_by = 1,

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    altpll_component.clk1_phase_shift = "250000",

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    altpll_component.compensate_clock = "CLK0",

11
    altpll_component.inclk0_input_frequency = 20000,

Can someone highlights me this issue please? it's possible to do it 
using one clock ?
Best regards
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #3881518
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jeorges FrenchRivera wrote:
> assign  oSCLK    =  (go_en)? iCLK:1;
This gated clock is not a good design practice. If a clock has to be 
output to a FPGA pin, a DDR regigster should be used...

> but i don't understand the sample code of the ADC module given by
> terasic.
Did you try it? If so: what specific part do you not understand?

> These clocks as generated as follows:
I cannot find them there. The only entry of those signals is the port 
list of the ADC_CTRL module.

> it's possible to do it using one clock ?
Usually it the best way to use only one clock and only one edge of 
that clock. Using the other edge of that clock also means a physically 
doubling of the clock frequency. But here it is senseless, because a PLL 
is used and this could be easily configured to deliver the double 
clock...
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jeorges FrenchRivera Guest #3881562
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Thank you Miler for you reply.

>I cannot find them there. The only entry of those signals is the port
>list of the ADC_CTRL module.
You are right i forget to precise that the clocks generation is given in 
another file
1
//=======================================================

2
//  REG/WIRE declarations

3
//=======================================================

4
wire            wSPI_CLK;

5
wire            wSPI_CLK_n;

6


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//=======================================================

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//  Structural coding

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//=======================================================

10
SPIPLL    U0  (

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            .inclk0(CLOCK_50),

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            .c0(wSPI_CLK),

13
            .c1(wSPI_CLK_n)

14
          );

15


16
ADC_CTRL    U1  (

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            .iRST(KEY[0]),

18
            .iCLK(wSPI_CLK),

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            .iCLK_n(wSPI_CLK_n),

20
            .iGO(KEY[1]),

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            .iCH(SW[2:0]),

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            .oLED(LED),

23
            

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            .oDIN(ADC_SADDR),

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            .oCS_n(ADC_CS_N),

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            .oSCLK(ADC_SCLK),

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            .iDOUT(ADC_SDAT)

28
          );

29


30


31
endmodule


>Did you try it? If so: what specific part do you not understand?
Yes i tried it and it works but when i compare with the datasheet of 
ADC, i didn't understand cont and m_cont values and the aims to use two 
Clocks.
I hope that it's clear for you.

Best regards
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