Hi everyone,
I have a DE0_NANO board, i try to use the ADC(ADC128S022) integrated in
the board but i don't understand the sample code of the ADC module given
by terasic.
the code is below :
1
moduleADC_CTRL(
2
iRST,
3
iCLK,
4
iCLK_n,
5
iGO,
6
iCH,
7
oLED,
8
9
oDIN,
10
oCS_n,
11
oSCLK,
12
iDOUT
13
);
14
15
inputiRST;
16
inputiCLK;
17
inputiCLK_n;
18
inputiGO;
19
input[2:0]iCH;
20
output[7:0]oLED;
21
22
outputoDIN;
23
outputoCS_n;
24
outputoSCLK;
25
inputiDOUT;
26
27
regdata;
28
reggo_en;
29
wire[2:0]ch_sel;
30
regsclk;
31
reg[3:0]cont;
32
reg[3:0]m_cont;
33
reg[11:0]adc_data;
34
reg[7:0]led;
35
36
assignoCS_n=~go_en;
37
assignoSCLK=(go_en)?iCLK:1;
38
assignoDIN=data;
39
assignch_sel=iCH;
40
assignoLED=led;
41
42
always@(posedgeiGOornegedgeiRST)
43
begin
44
if(!iRST)
45
go_en<=0;
46
else
47
begin
48
if(iGO)
49
go_en<=1;
50
end
51
end
52
53
always@(posedgeiCLKornegedgego_en)
54
begin
55
if(!go_en)
56
cont<=0;
57
else
58
begin
59
if(iCLK)
60
cont<=cont+1;
61
end
62
end
63
64
always@(posedgeiCLK_n)
65
begin
66
if(iCLK_n)
67
m_cont<=cont;
68
end
69
70
always@(posedgeiCLK_nornegedgego_en)
71
begin
72
if(!go_en)
73
data<=0;
74
else
75
begin
76
if(iCLK_n)
77
begin
78
if(cont==2)
79
data<=iCH[2];
80
elseif(cont==3)
81
data<=iCH[1];
82
elseif(cont==4)
83
data<=iCH[0];
84
else
85
data<=0;
86
end
87
end
88
end
89
90
always@(posedgeiCLKornegedgego_en)
91
begin
92
if(!go_en)
93
begin
94
adc_data<=0;
95
led<=8'h00;
96
end
97
else
98
begin
99
if(iCLK)
100
begin
101
if(m_cont==4)
102
adc_data[11]<=iDOUT;
103
elseif(m_cont==5)
104
adc_data[10]<=iDOUT;
105
elseif(m_cont==6)
106
adc_data[9]<=iDOUT;
107
elseif(m_cont==7)
108
adc_data[8]<=iDOUT;
109
elseif(m_cont==8)
110
adc_data[7]<=iDOUT;
111
elseif(m_cont==9)
112
adc_data[6]<=iDOUT;
113
elseif(m_cont==10)
114
adc_data[5]<=iDOUT;
115
elseif(m_cont==11)
116
adc_data[4]<=iDOUT;
117
elseif(m_cont==12)
118
adc_data[3]<=iDOUT;
119
elseif(m_cont==13)
120
adc_data[2]<=iDOUT;
121
elseif(m_cont==14)
122
adc_data[1]<=iDOUT;
123
elseif(m_cont==15)
124
adc_data[0]<=iDOUT;
125
elseif(m_cont==1)
126
led<=adc_data[11:4];
127
end
128
end
129
end
130
131
endmodule
I don't understand why we use two clocks:iCLK,iCLK_n,
These clocks as generated as follows:
1
altpll_component.bandwidth_type="AUTO",
2
altpll_component.clk0_divide_by=25,
3
altpll_component.clk0_duty_cycle=50,
4
altpll_component.clk0_multiply_by=1,
5
altpll_component.clk0_phase_shift="0",
6
altpll_component.clk1_divide_by=25,
7
altpll_component.clk1_duty_cycle=50,
8
altpll_component.clk1_multiply_by=1,
9
altpll_component.clk1_phase_shift="250000",
10
altpll_component.compensate_clock="CLK0",
11
altpll_component.inclk0_input_frequency=20000,
Can someone highlights me this issue please? it's possible to do it
using one clock ?
Best regards
jeorges FrenchRivera wrote:> assign oSCLK = (go_en)? iCLK:1;
This gated clock is not a good design practice. If a clock has to be
output to a FPGA pin, a DDR regigster should be used...
> but i don't understand the sample code of the ADC module given by> terasic.
Did you try it? If so: what specific part do you not understand?
> These clocks as generated as follows:
I cannot find them there. The only entry of those signals is the port
list of the ADC_CTRL module.
> it's possible to do it using one clock ?
Usually it the best way to use only one clock and only one edge of
that clock. Using the other edge of that clock also means a physically
doubling of the clock frequency. But here it is senseless, because a PLL
is used and this could be easily configured to deliver the double
clock...
Thank you Miler for you reply.
>I cannot find them there. The only entry of those signals is the port>list of the ADC_CTRL module.
You are right i forget to precise that the clocks generation is given in
another file
>Did you try it? If so: what specific part do you not understand?
Yes i tried it and it works but when i compare with the datasheet of
ADC, i didn't understand cont and m_cont values and the aims to use two
Clocks.
I hope that it's clear for you.
Best regards
jeorges FrenchRivera wrote:> and the aims to use two Clocks.
"Ease" of design? Or stupidity? Who knows...
As I said the design could be easily made with only one clock with the
doubled frequency. Then there would aslo be no need for the gated SCLK.