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Forum: FPGA, VHDL & Verilog Two digit BCD adder


Author: Yhx Yhx (Company: Yhx) (yhx)
Posted on:
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WHY can't operation carry?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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Yhx Yhx wrote:
> f.png
Why sourcecode as picture? Do it this way:
[vhdl]
   your VHDL code
[/vhdl]
Where's the code for the full adder? Is it working?
Why do you have a full adder as a component, and why do you also use the 
'+' operator?

> f2.png
What are the signals in there? You should have the signal names in the 
screenshot? Or ist is a riddle for us to assign the signals to the 
values?

: Edited by Moderator
Author: Yhx Yhx (Company: Yhx) (yhx)
Posted on:
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I'm sorry
The "BCD.txt" is my code, and my full adder is work correctly.
What should i revise for this problem?
Thanks a lot.

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