WHY can't operation carry?
Yhx Yhx wrote: > f.png Why sourcecode as picture? Do it this way:
1 | [vhdl] |
2 | your VHDL code |
3 | [/vhdl] |
Where's the code for the full adder? Is it working?
Why do you have a full adder as a component, and why do you also use the
'+' operator?
> f2.png
What are the signals in there? You should have the signal names in the
screenshot? Or ist is a riddle for us to assign the signals to the
values?
:
Edited by Moderator
I'm sorry The "BCD.txt" is my code, and my full adder is work correctly. What should i revise for this problem? Thanks a lot.
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