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This is my code (to design Carry Look Ahead Adder) library ieee; use ieee.std_logic_1164.all; entity CLAdder is port(A,B: IN std_logic; Cin: IN std_logic; Sum: OUT std_logic_vector(3 DOWNTO 0); Cout,G,P: OUT std_logic); end CLAdder; architecture behavior of CLAdder is signal carryGen: std_logic_vector(3 DOWNTO 0); signal carryProp: std_logic_vector(3 DOWNTO 0); signal Sumation: std_logic_vector(3 DOWNTO 0); signal carryIns: std_logic_vector(3 DOWNTO 0); begin  behavior Sumation(0) <= A(0) xor B(0) xor Cin; carryGen(0) <= A(0) and B(0); carryProp(0) <= A(0) or B(0); carryIns(0) <= carryGen(0) or (carryProp(0) and Cin); Sumation(1) <= A(1) xor B(1) xor carryIns(0); carryGen(1) <= A(1) and B(1); carryProp(1) <= A(1) or B(1); carryIns(1) <= carryGen(1) or (carryProp(1) and carryIns(0)); Sumation(2) <= A(2) xor B(2) xor CarryIns(1); carryGen(2) <= A(2) and B(2); carryProp(2) <= A(2) or B(2); carryIns(2) <= carryGen(2) or (carryProp(2) and carryIns(1)); Sumation(3) <= A(3) xor B(3) xor CarryIns(2); carryGen(3) <= A(3) and B(3); carryProp(3) <= A(3) or B(3); carryIns(3) <= carryGen(3) or (carryProp(3) and carryIns(2)); G <= carryGen(3) or (carryGen(2) and carryProp(3)) or (carryGen(1) and carryProp(2) and carryProp(3)) or (carryGen(0) and carryProp(1) and carryProp(2) and carryProp(3)); P <= carryProp(0) and carryProp(1) and carryProp(2) and carryProp(3); end behavior; When using vhdlan to verify and check for errors I get 24 errors at each of the signal assignments in the behavior body going like Error[OVBADAPPLIED] Illegal prefix CLAdder.vhd, 36 BEHAVIOR carryProp(3) <= A(3) or B(3); ^ Prefix of name cannot be interpreted as a subprogram or array. This is just one of them. The rest are all the same but for different assignments. I cannot figure out what is wrong here. Please help.
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A and B should be 4bit vectors...
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I have written a VHDL code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. I'm attaching the code with this. Also attaching the generated RTL scheatic.
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REKHA V P wrote: > I have written a VHDL code for a number of cascaded mux stages. Start a NEW thread for a NEW question! And post VHDL code as *.vhdl file. And don't use all the libraries you can find in the universe in one VHDL module:
use IEEE.STD_LOGIC_ARITH.ALL;  never use IEEE.STD_LOGIC_UNSIGNED.ALL;  ever ... use IEEE.numeric_std.all;  use those three together! 
> But I can't implement the test bench waveform.
What problems do you encounter?
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