EmbDev.net

Forum: FPGA, VHDL & Verilog Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification


Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
Author: Jay (Guest)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
Hi Guys,

I was asked to prepare a presentation on the topic below:

Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware 
verification

Someone plz educate me. I am new to these.

Thank you.

Regards,
Jay

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
Author: amigo (Guest)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
what of bull is that to ask a newbe to create a presentation?

dude, it is YOUR task to find information, not let others search the net 
for it

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.