EmbDev.net

Forum: FPGA, VHDL & Verilog Best FPGA setup for AES encryption


Best FPGA setup for AES encryption
von (unknown) (Guest)

Rate this post
0 ▲ useful
▼ not useful 
What is the optimal FPGA size and what kind of memory should I use for 
implementing AES encryption? For example: can I get 1Mbps speeds from 
100k FPGA and how is this speed dependant from FPGA-s size?

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.