16 bit PISO register

Omar Rashad Guest #3859193
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I am trying to write the VHDL code for a synchronous 16 bit register 
(SIPO, asynchronous reset) to use it as a component in another Serial 
Multiplier code.

I have been struggling with 'U' output on my signal:

code:
1
library ieee;

2
use ieee.std_logic_1164.all;

3


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entity ShiftRegister is

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  port(A: IN std_logic_vector (15 downto 0);

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       clk,load,reset: IN std_logic;

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       Y: OUT std_logic);

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end ShiftRegister;

9


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architecture behavior of ShiftRegister is

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signal tmp: std_logic_vector(15 downto 0);

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begin

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tmp <= (others => '0');

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process (reset,clk)

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begin

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  if (reset = '1') then

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    Y <= '0';

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  end if;

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end process;

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process (load, A)

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begin

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  if (load = '1') then

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    tmp <= A;

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  else 

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    tmp <= (others => '0');

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  end if;

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end process;

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process (clk)

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begin

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if (clk = '1' and clk'EVENT) then

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  Y <= tmp(0);

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  tmp <= '0' & tmp(15 downto 1);

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end if;

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end process;

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end behavior;


Test Bench:
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library ieee;

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use ieee.std_logic_1164.all;

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entity tb_ShiftRegister is

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end tb_ShiftRegister;

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architecture behavior of tb_ShiftRegister is

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component ShiftRegister

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  port(A: IN std_logic_vector(15 downto 0);

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       clk,load,reset: IN std_logic;

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       Y: OUT std_logic);

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end component;

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signal A: std_logic_vector (15 downto 0);

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signal clk,load,reset,Y: std_logic:= '0';

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begin

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clk <= not clk after 10 ns;

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DUT: ShiftRegister port map (A,clk,load,reset,Y);

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process

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begin

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  wait for 0 ns;

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  reset <= '1'; load <= '1'; A <= "1010101010101010";

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  wait for 320 ns;

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  --A <= "1111000011110000";

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  --wait for 320 ns;

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end process;

28
end behavior;
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Omar Rashad Guest #3859355
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Here is what I've managed to code (still no go). The processes do not 
seem to return different Y values but I still get 'U'

1
library ieee;

2
use ieee.std_logic_1164.all;

3


4
entity ShiftRegister is

5
  port(A: IN std_logic_vector (15 downto 0);

6
       clk,load,reset: IN std_logic;

7
       Y: OUT std_logic);

8
end ShiftRegister;

9


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architecture behavior of ShiftRegister is

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signal tmp: std_logic_vector(15 downto 0):=(others => '0');

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signal F: std_logic:='0';

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begin

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--tmp <= (others => '0');

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process (reset,clk,A)

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begin

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if (reset = '1') then

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  F <= '0';

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elsif (clk = '1' and clk'event) then

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  F <= tmp(0);

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  tmp <= '0' & tmp(15 downto 1);

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else

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  F <= F;

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end if;

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end process;

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process (load,A)

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begin

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if (load = '1') then

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  tmp <= A;

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end if;

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end process;

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Y <= F;

35


36
end behavior;
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Lothar M. Moderator (Company: Titel) #3859359
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Omar Rashad wrote:
> but I still get 'U'
Now the question arises: What is 'U'?
'U'ndefined, 'U'seless, 'U'ncertain, 'U'ninitilized?

1
   reset <= '1'; load <= '1'; A <= "1010101010101010";

2
   wait for 320 ns;

Shouldn't you do anything with load and reset afterwards?

After having managed that you will encounter serious problems with this 
here:
1
architecture behavior of ShiftRegister is

2
signal tmp: std_logic_vector(15 downto 0);

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begin

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tmp <= (others => '0');            -- tmp is ALWAYS reset to all zero!

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process (reset,clk)

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begin

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  if (reset = '1') then

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    Y <= '0';

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  end if;

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end process;

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process (load, A)

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begin

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  if (load = '1') then

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    tmp <= A;                      -- ADDITIONALLY sometimes tmp gets the value of A

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  else 

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    tmp <= (others => '0');        -- if not is is reset to zero ONCE MORE

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  end if;

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end process;

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process (clk)

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begin

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if (clk = '1' and clk'EVENT) then

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  Y <= tmp(0);                                 

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  tmp <= '0' & tmp(15 downto 1);   -- ADDITIONALLY sometimes its shifted with a clock

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end if;

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end process;

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end behavior;

All in all: you drive tmp from three sources. That will not work! it 
will result in a collision. And
BTW: the very same is for Y! It is driven from two sources...
In fact you cannot reset Y because its the very same signal as tmp(0)!
Why should you need here a reset signal at all?

Try it that way and think hard about it:
1
architecture behavior of ShiftRegister is

2
  signal tmp: std_logic_vector(15 downto 0) := (others=>'0');

3
begin

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  process (clk,load,A)

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  begin

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    if (load = '1') then

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      tmp <= A;

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    elsif (clk = '1' and clk'EVENT) then                              

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      tmp <= '0' & tmp(15 downto 1);

10
    end if;

11
  end process;

12


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  Y <= tmp(0);                                 

14
end behavior;
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Omar Rashad Guest #3859371
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Aren't all processes treated as concurrent statements within 
architecure? So only when one of the elements in the sensitivity list 
changes do they run again, correct? That means only processes with 
changes in their SL will get re-evaluated. Do I understand this 
correctly?

And the code that you provided (theoretically, I cannot simulate it now) 
does not work as intended. This is because tmp is reset to A everytime 
the process runs so we won't truly get the serial output of A, just 
continuous A(0)'s.
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P. K. #3859414
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Omar Rashad wrote:
> So only when one of the elements in the sensitivity list
> changes do they run again, correct? That means only processes with
> changes in their SL will get re-evaluated. Do I understand this
> correctly?

From the point of view how the Simulator calculates the result of each 
process this is correct, but: The other processes that are not 
re-evaluated still drive the signals (with the same not re-evaluated 
values as before).

In fact, it is only the simulator that makes use of sensitivity lists 
(to know when it needs to calculate new values). The hardware that 
results from synthesis just permanently "is there".
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Lothar M. Moderator (Company: Titel) #3859759
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Omar Rashad wrote:
> Do I understand this correctly?
Just for the simulation this is (nearly) correct. But in hardware each 
process is realized in parallel to each other process and "it" will 
drive its value all the time...

> And the code that you provided (theoretically, I cannot simulate it now)
> does not work as intended.
It works as far as my intention was: I load a value int the shift 
register by assigning a value to A and setting load to '1'. AFTERWARDS 
i set load to '0' and start clocking the data out. Got the trick?

And do you remeber my question:
Lothar Miller wrote:
>  reset <= '1'; load <= '1'; A <= "1010101010101010";
>  wait for 320 ns;
> Shouldn't you do anything with load and reset afterwards?
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Omar Rashad Guest #3860320
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By assignment I was referring to my assignment

Reset clears the output to zero regardless of load. When reset is zero, 
content is zero if load is zero and is filled with Din when load is one. 
That is why load and A are in a separate process that is sensitive to 
both but not reset or clock.
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Lothar M. Moderator (Company: Titel) #3860433
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Omar Rashad wrote:
> When reset is zero, content is zero if load is zero and is filled with
> Din when load is one.
A very unusual behavior. For a pity there is no hardware inside a FPGA 
able to handle such behavior...

> That is why load and A are in a separate process
> that is sensitive to both but not reset or clock.
You think the wrong way! You cannot control hardware stucture with the 
sensitivity list. The sensitivity lust is only relevant for the 
simulator.
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Lothar M. Moderator (Company: Titel) #3860821
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Ok, here we go.
My spec is:
1. when load is '1' then load the vector A to the shift register
2. when load is '0' then shift out the data bit LSB first through Y
And this is the result:
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3


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entity Piso is

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    Port ( clk :  in   STD_LOGIC;

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           load : in   STD_LOGIC;

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           A :    in   STD_LOGIC_VECTOR (15 downto 0);

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           Y :    out  STD_LOGIC);

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end Piso;

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architecture Behavioral of Piso is

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  signal sr: std_logic_vector(15 downto 0) := (others=>'0');

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begin

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  process (clk,load,A)

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  begin

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    if (load = '1') then

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      sr <= A;

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    elsif rising_edge(clk) then

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      sr <= '0' & sr(15 downto 1);

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    end if;

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  end process;

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  Y <= sr(0);      

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end Behavioral;


Using this testbench I get the waveform in the screenshot:
1
LIBRARY ieee;

2
USE ieee.std_logic_1164.ALL;

3
 

4
ENTITY tb_piso IS

5
END tb_piso;

6
 

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ARCHITECTURE behavior OF tb_piso IS 

8
 

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    COMPONENT Piso

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    PORT(

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         clk : IN  std_logic;

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         load : IN  std_logic;

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         A : IN  std_logic_vector(15 downto 0);

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         Y : OUT  std_logic

15
        );

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    END COMPONENT;

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   signal clk : std_logic := '0';

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   signal load : std_logic := '0';

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   signal A : std_logic_vector(15 downto 0) := (others => '0');

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   signal Y : std_logic;

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BEGIN

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   uut: Piso PORT MAP (

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          clk => clk,

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          load => load,

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          A => A,

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          Y => Y

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        );

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   clk <= not clk after 5 ns;

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   process  begin    

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      A <= x"5555";

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      load <= '1';

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      wait for 15ns;

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      load <= '0';

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      wait for 200ns;

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      A <= x"CCCC";

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      load <= '1';

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      wait for 15ns;

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      load <= '0';

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      wait for 200ns;

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      A <= x"F0F0";

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      load <= '1';

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      wait for 15ns;

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      load <= '0';

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      wait for 200ns;

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      wait;

54
   end process;

55


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END;


The PISO is synthesizeable and results in 16 D-Flipflops with 
asynchronous clrear and preset inputs, which are controlled from A with 
a little glue logic. See the RTL schematic for this result...
Attached files:
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