Omar Rashad wrote:
> but I still get 'U'
Now the question arises: What is 'U'?
'U'ndefined, 'U'seless, 'U'ncertain, 'U'ninitilized?
1 | reset <= '1'; load <= '1'; A <= "1010101010101010";
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2 | wait for 320 ns;
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Shouldn't you do anything with load and reset afterwards?
After having managed that you will encounter serious problems with this
here:
1 | architecture behavior of ShiftRegister is
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2 | signal tmp: std_logic_vector(15 downto 0);
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3 | begin
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4 | tmp <= (others => '0'); -- tmp is ALWAYS reset to all zero!
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5 |
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6 | process (reset,clk)
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7 | begin
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8 | if (reset = '1') then
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9 | Y <= '0';
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10 | end if;
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11 | end process;
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12 |
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13 | process (load, A)
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14 | begin
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15 | if (load = '1') then
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16 | tmp <= A; -- ADDITIONALLY sometimes tmp gets the value of A
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17 | else
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18 | tmp <= (others => '0'); -- if not is is reset to zero ONCE MORE
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19 | end if;
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20 | end process;
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21 |
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22 | process (clk)
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23 | begin
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24 | if (clk = '1' and clk'EVENT) then
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25 | Y <= tmp(0);
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26 | tmp <= '0' & tmp(15 downto 1); -- ADDITIONALLY sometimes its shifted with a clock
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27 | end if;
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28 | end process;
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29 |
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30 | end behavior;
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All in all: you drive tmp from three sources. That will not work! it
will result in a collision. And
BTW: the very same is for Y! It is driven from two sources...
In fact you cannot reset Y because its the very same signal as tmp(0)!
Why should you need here a reset signal at all?
Try it that way and think hard about it:
1 | architecture behavior of ShiftRegister is
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2 | signal tmp: std_logic_vector(15 downto 0) := (others=>'0');
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3 | begin
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4 | process (clk,load,A)
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5 | begin
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6 | if (load = '1') then
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7 | tmp <= A;
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8 | elsif (clk = '1' and clk'EVENT) then
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9 | tmp <= '0' & tmp(15 downto 1);
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10 | end if;
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11 | end process;
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12 |
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13 | Y <= tmp(0);
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14 | end behavior;
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