I am not able to do the increment and the testbench for this code.

Question:

A system has a 3-bit input D_IN which is read in at every positive edge 
of a clock input CLK. If the current D_IN is greater than the previous 
D_IN by at least 2, a 3-bit output Count is incremented. If D_IN is 0 
for 3 consecutive CLK cycles, the count is reset. When Count reaches 6, 
the system will assert an output Alarm and the Count will not increase 
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles.

Test case:

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Clk  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

2

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D_IN 0 0 0 2 4 7 6 0 2 4  6  3  5  7  0  0  0  0

code

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.NUMERIC_STD.ALL;

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entity johnson_counter is

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port ( 

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    D_in  : in std_logic_vector(2 downto 0);

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    alarm : out std_logic;

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    CLK_I : in std_logic

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    );

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end johnson_counter;

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architecture Behavioral of johnson_counter is

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signal xnew, xold, count1, count2: unsigned(2 downto 0):=(others => '0');

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begin

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process(CLK_I)

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begin

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if( rising_edge(CLK_I) ) then

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 xnew <= std_logic_vector(unsigned(D_in));

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 xnew <= xnew - "010";

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    if (xnew => xold) then

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        count1 <= count1 + "1";

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    if(xnew = 0) then

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            count2 <= count2 + "1";

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      if(xnew /= 0) then

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            count2 <= "0";

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      if(count2 = "011") then

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            alarm <= "1";

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    end if;

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      end if;

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      end if;

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      end if;

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end if;

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end process;

Icy Snow wrote:
> code
Whats the problem with it? Whats the problem at all?

Is this any good for:
> xold
It isn't used in the code, so it must be obsolete...

This will create an error:

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  xnew <= std_logic_vector(unsigned(D_in)); -- what type is xnew?

This does not behave like you desired it:

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 process(CLK_I)

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 begin

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 if( rising_edge(CLK_I) ) then

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   xnew <= std_logic_vector(unsigned(D_in));

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   xnew <= xnew - "010";

You know about the behaviour of signal in a process?
You will find out, that the fist assignment is simply ignored, and 
therefore xnew is simply a down-counter with a decrement of 2. In fact 
you could write this process without any change in behaviour like this:

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 process(CLK_I)

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 begin

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 if( rising_edge(CLK_I) ) then

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   xnew <= xnew - "010";

> Test case:
> Clk  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
> D_IN 0 0 0 2 4 7 6 0 2 4  6  3  5  7  0  0  0  0
Did you create a test bench out of this data? How does it look like?


All in all you are a lucky man: you don't have to do last milleniums 
technology like structural description of a multiplier built of 
halfadders. Insted you got a problem fairly near to what is the daily 
work of a FPGA designer.

BTW:
Did you see this above the edit box?

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Formatting options

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    [vhdl]VHDL code[/vhdl]