Hello. I do not understand, how i can do next thing. My block have 3 input ports and 1 output port. Input ports are fast_clock,slow_clock,enable. Output port is clock_out. So, i want to change a front of slow_clock in time of change "enable" (it's changing from 0 to 1 and have it value all time long) or 1-3 times of "fast_clock". Front changing's rule is: if slow_clock = '1' then clock_out = '1' else clock_out = not(slow_clock). My blocks after this blocks must feel changing a front ( in VHDL language: rising_edge(clk) ). I want to get "clock_out" with the same frequancy that "slow_clock", but if "enable" changing from '0' to '1' or after 1-3 times of "fast_clock" my next blocks must feel changing from low front to high front. I tried to do it with next code:
1 | process(enb,fast_clock,slow_clock) |
2 | begin
|
3 | if rising_edge(fast_clock) then |
4 | if enb='1' then |
5 | if slow_clock='1' then |
6 | clock_out <= slow_clock; |
7 | elsif slow_clock='0' then |
8 | clk_out <= not(slow_clock); |
9 | end if; |
10 | else
|
11 | clk_out <= '0'; |
12 | end if; |
13 | end if; |
14 | end process; |
Your current VHDL code can be reduced to:
1 | process(enb,fast_clock) |
2 | begin
|
3 | if rising_edge(fast_clock) then |
4 | clk_out <= enb; |
5 | end if; |
6 | end process; |
Nobody understands what you really want to do.
:
Edited by User
Andreas S. wrote: > Your current VHDL code can be reduced to: ... Even this can be reduced further on: take enb out of the sensitivity list. A clock would be enough... Dima U. wrote: > So, i want to change a front of slow_clock in time of change "enable" > (it's changing from 0 to 1 and have it value all time long) or 1-3 times > of "fast_clock". Uhhmmmm, could you draw that as a schematic or a block diagram? Then it is easy to describe with VHDL (as VHDL is a description language). Or maybe you can draw a timing diagram where it can be seen, what shlud happen.
Lothar M. wrote: > Dima U. wrote: >> So, i want to change a front of slow_clock in time of change "enable" >> (it's changing from 0 to 1 and have it value all time long) or 1-3 times >> of "fast_clock". > Uhhmmmm, could you draw that as a schematic or a block diagram? Then it > is easy to describe with VHDL (as VHDL is a description language). > Or maybe you can draw a timing diagram where it can be seen, what > shlud happen. I have 2 independent data streams, and i must start to send both synch with special mark of time. The mark has 100 ns high front and 1 second has low front; and it's periodic signal. Freq.-s of both signals is non-constant. I try to do next thing: when the first high front of mark come i make "enable" signal. After changing the "enable" signal starts to work some blocks, and both of streams i'm writing in RAM (not at all 1 second long,of course). When next mark coming i make "enable" for reading from RAM and in start post's i wrote my attempt to generate clock for reading. Timing diagram here. /Mark of time/: 100 ns high front and 1 second has low front signal; enable_1 - blocks start to work from this signal; write_enable - enable to write RAM; read_enable - enable to read RAM; clock for reading - (red color) this signal i want to use for reading from RAM and it i tried in the first post. And finally, out data - one (for simplify) data stream what i have.